Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T4,T38
1	1	Covered	T3,T21,T22

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T20,T50
1	1	Covered	T9,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T10,T20
1	0	Covered	T4,T5,T32

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T21,T10,T20
1	Covered	T4,T5,T32

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T21,T10,T20
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T21,T10,T4
1	Covered	T4,T5,T32

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T11,T15
AutoCaptGenCnt	143	Covered	T9,T11,T15
AutoCaptReseedCnt	141	Covered	T9,T11,T15
AutoDispatch	125	Covered	T9,T11,T15
AutoFirstAckWait	119	Covered	T9,T11,T15
AutoLoadIns	69	Covered	T9,T10,T11
AutoSendGenCmd	150	Covered	T9,T11,T15
AutoSendReseedCmd	162	Covered	T9,T11,T15
BootDone	98	Covered	T3,T22,T23
BootGenAckWait	90	Covered	T3,T22,T23
BootInsAckWait	80	Covered	T3,T21,T22
BootLoadGen	85	Covered	T3,T22,T23
BootLoadIns	65	Covered	T3,T21,T22
BootLoadUni	102	Covered	T3,T22,T49
BootPulse	94	Covered	T3,T22,T23
BootUniAckWait	107	Covered	T3,T22,T49
Error	188	Covered	T4,T5,T32
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T21,T10,T20
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T11,T15
AutoAckWait->Error	188	Covered	T102,T103,T104
AutoAckWait->Idle	211	Covered	T11,T50,T60
AutoAckWait->RejectCsrngEntropy	188	Covered	T41,T79,T105
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T9,T11,T15
AutoCaptGenCnt->Error	188	Covered	T106
AutoCaptGenCnt->Idle	211	Covered	T107,T108,T109
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T93,T110,T111
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T11,T15
AutoCaptReseedCnt->Error	188	Covered	T112,T113,T114
AutoCaptReseedCnt->Idle	211	Covered	T115,T116,T117
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T118,T119,T120
AutoDispatch->AutoCaptGenCnt	143	Covered	T9,T11,T15
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T11,T15
AutoDispatch->Error	188	Covered	T121,T122
AutoDispatch->Idle	138	Covered	T9,T11,T15
AutoDispatch->RejectCsrngEntropy	188	Covered	T123,T124,T125
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T11,T15
AutoFirstAckWait->Error	188	Covered	T126,T127
AutoFirstAckWait->Idle	211	Covered	T89,T128,T129
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T98,T97,T130
AutoLoadIns->AutoFirstAckWait	119	Covered	T9,T11,T15
AutoLoadIns->Error	188	Covered	T6,T8,T131
AutoLoadIns->Idle	211	Covered	T41,T63,T93
AutoLoadIns->RejectCsrngEntropy	188	Covered	T10,T20,T54
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T11,T15
AutoSendGenCmd->Error	188	Covered	T132
AutoSendGenCmd->Idle	211	Covered	T77,T133,T134
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T91,T92,T95
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T11,T15
AutoSendReseedCmd->Error	188	Covered	T135
AutoSendReseedCmd->Idle	211	Covered	T50,T136,T137
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T138,T139,T140
BootDone->BootLoadUni	102	Covered	T3,T22,T49
BootDone->Error	188	Covered	T141,T142
BootDone->Idle	211	Covered	T23,T143,T144
BootDone->RejectCsrngEntropy	188	Covered	T69,T145,T146
BootGenAckWait->BootPulse	94	Covered	T3,T22,T23
BootGenAckWait->Error	188	Covered	T147,T148,T149
BootGenAckWait->Idle	211	Covered	T150,T151,T152
BootGenAckWait->RejectCsrngEntropy	188	Covered	T153,T154,T155
BootInsAckWait->BootLoadGen	85	Covered	T3,T22,T23
BootInsAckWait->Error	188	Covered	T156,T157,T158
BootInsAckWait->Idle	211	Covered	T4,T74,T17
BootInsAckWait->RejectCsrngEntropy	188	Covered	T21,T75,T159
BootLoadGen->BootGenAckWait	90	Covered	T3,T22,T23
BootLoadGen->Error	188	Covered	T17,T160,T161
BootLoadGen->Idle	211	Covered	T80,T162,T163
BootLoadGen->RejectCsrngEntropy	188	Covered	T164,T165,T166
BootLoadIns->BootInsAckWait	80	Covered	T3,T21,T22
BootLoadIns->Error	188	Covered	T4,T167,T168
BootLoadIns->Idle	211	Covered	T169,T170,T171
BootLoadIns->RejectCsrngEntropy	188	Covered	T63,T172,T173
BootLoadUni->BootUniAckWait	107	Covered	T3,T22,T49
BootLoadUni->Error	188	Covered	T47,T174,T175
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T78,T176,T177
BootPulse->BootDone	98	Covered	T3,T22,T23
BootPulse->Error	188	Covered	T178
BootPulse->Idle	211	Covered	T38,T179,T180
BootPulse->RejectCsrngEntropy	188	Covered	T53,T181,T182
BootUniAckWait->Error	188	Covered	T183,T184,T185
BootUniAckWait->Idle	112	Covered	T3,T22,T49
BootUniAckWait->RejectCsrngEntropy	188	Covered	T186,T187,T188
Idle->AutoLoadIns	69	Covered	T9,T10,T11
Idle->BootLoadIns	65	Covered	T3,T21,T22
Idle->Error	188	Covered	T16,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T21,T41,T53
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T5,T64,T45
RejectCsrngEntropy->Idle	211	Covered	T21,T10,T20
SWPortMode->Error	188	Covered	T32,T16,T189
SWPortMode->Idle	211	Covered	T1,T21,T10
SWPortMode->RejectCsrngEntropy	188	Covered	T10,T20,T5

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T23
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T23
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T23
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T23
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T22,T49
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T23,T4,T38
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T49
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T22,T49
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T22,T49
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T11,T15
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T9,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T11,T15
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T15,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T11,T15
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T11,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T15,T12
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T10,T20
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T57,T84

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T5,T32
1	0	1	-	Not Covered
1	0	0	-	Covered	T21,T10,T20
0	-	-	1	Covered	T21,T10,T23
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	249757816	125403	0	0
FpvSecCmErrorStEscalate_A	249757816	126187	0	0
u_state_regs_A	249721003	249559722	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	125403	0	0
T4	1892	1104	0	0
T5	1472	820	0	0
T6	0	1128	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	6977	0	0
T17	0	1072	0	0
T20	1768	0	0	0
T32	0	598	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	560	0	0
T64	0	1110	0	0
T147	0	350	0	0
T189	0	608	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	126187	0	0
T4	1892	1105	0	0
T5	1472	821	0	0
T6	0	1129	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7107	0	0
T17	0	1073	0	0
T20	1768	0	0	0
T32	0	599	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	561	0	0
T64	0	1111	0	0
T147	0	351	0	0
T189	0	609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249721003	249559722	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1715	1519	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0