Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T22
DataWait	75	Covered	T1,T2,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T38
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T22
DataWait->AckPls	80	Covered	T1,T2,T22
DataWait->Disabled	107	Covered	T74,T77,T190
DataWait->Error	99	Covered	T64,T57,T17
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T191,T169,T170
EndPointClear->Error	99	Covered	T4,T16,T192
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T22
Idle->Disabled	107	Covered	T1,T21,T10
Idle->Error	99	Covered	T5,T32,T64

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T22
Idle	-	1	0	-	Covered	T1,T2,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T22
DataWait	-	-	-	0	Covered	T1,T2,T22
AckPls	-	-	-	-	Covered	T1,T2,T22
Error	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	Covered	T5,T32,T64

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T32
0	1	Covered	T21,T10,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1748304712	886671	0	0
FpvSecCmErrorStEscalate_A	1748304712	892159	0	0
u_state_regs_A	1748267899	1747138932	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1748304712	886671	0	0
T4	13244	7728	0	0
T5	10304	5690	0	0
T6	0	7846	0	0
T11	13069	0	0	0
T12	15512	0	0	0
T15	15540	0	0	0
T16	0	48839	0	0
T17	0	7504	0	0
T20	12376	0	0	0
T32	0	4136	0	0
T38	5691	0	0	0
T40	15337	0	0	0
T49	14693	0	0	0
T50	19516	0	0	0
T57	0	4270	0	0
T64	0	7720	0	0
T147	0	2400	0	0
T189	0	4206	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1748304712	892159	0	0
T4	13244	7735	0	0
T5	10304	5697	0	0
T6	0	7853	0	0
T11	13069	0	0	0
T12	15512	0	0	0
T15	15540	0	0	0
T16	0	49749	0	0
T17	0	7511	0	0
T20	12376	0	0	0
T32	0	4143	0	0
T38	5691	0	0	0
T40	15337	0	0	0
T49	14693	0	0	0
T50	19516	0	0	0
T57	0	4277	0	0
T64	0	7727	0	0
T147	0	2407	0	0
T189	0	4213	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1748267899	1747138932	0	0
T1	3534825	3534776	0	0
T2	10248	9891	0	0
T3	10633	10185	0	0
T4	13067	11695	0	0
T9	33173	32585	0	0
T10	17374	16751	0	0
T21	13251	12866	0	0
T22	28721	28343	0	0
T23	7028	6482	0	0
T24	20216	19810	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T23,T15
DataWait	75	Covered	T22,T23,T15
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T23,T15
DataWait->AckPls	80	Covered	T22,T23,T15
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T64,T17,T183
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T191,T169,T170
EndPointClear->Error	99	Covered	T4,T16,T192
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T22,T23,T15
Idle->Disabled	107	Covered	T1,T21,T10
Idle->Error	99	Covered	T5,T32,T57

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T22,T23,T15
Idle	-	1	0	-	Covered	T22,T23,T15
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T22,T23,T15
DataWait	-	-	-	0	Covered	T22,T23,T15
AckPls	-	-	-	-	Covered	T22,T23,T15
Error	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T32
0	1	Covered	T21,T10,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	249757816	127053	0	0
FpvSecCmErrorStEscalate_A	249757816	127837	0	0
u_state_regs_A	249757816	249596535	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127053	0	0
T4	1892	1104	0	0
T5	1472	820	0	0
T6	0	1128	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	6977	0	0
T17	0	1072	0	0
T20	1768	0	0	0
T32	0	598	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	610	0	0
T64	0	1110	0	0
T147	0	350	0	0
T189	0	608	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127837	0	0
T4	1892	1105	0	0
T5	1472	821	0	0
T6	0	1129	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7107	0	0
T17	0	1073	0	0
T20	1768	0	0	0
T32	0	599	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	611	0	0
T64	0	1111	0	0
T147	0	351	0	0
T189	0	609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T22
DataWait	75	Covered	T1,T2,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T22
DataWait->AckPls	80	Covered	T1,T2,T22
DataWait->Disabled	107	Covered	T77,T134,T193
DataWait->Error	99	Covered	T57,T45,T194
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T191,T169,T170
EndPointClear->Error	99	Covered	T4,T16,T192
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T22
Idle->Disabled	107	Covered	T1,T21,T10
Idle->Error	99	Covered	T17,T43,T84

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T22
Idle	-	1	0	-	Covered	T1,T2,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T22
DataWait	-	-	-	0	Covered	T1,T2,T22
AckPls	-	-	-	-	Covered	T1,T2,T22
Error	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	Covered	T5,T32,T64

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T32
0	1	Covered	T21,T10,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	249757816	124353	0	0
FpvSecCmErrorStEscalate_A	249757816	125137	0	0
u_state_regs_A	249721003	249559722	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	124353	0	0
T4	1892	1104	0	0
T5	1472	770	0	0
T6	0	1078	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	6977	0	0
T17	0	1072	0	0
T20	1768	0	0	0
T32	0	548	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	610	0	0
T64	0	1060	0	0
T147	0	300	0	0
T189	0	558	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	125137	0	0
T4	1892	1105	0	0
T5	1472	771	0	0
T6	0	1079	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7107	0	0
T17	0	1073	0	0
T20	1768	0	0	0
T32	0	549	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	611	0	0
T64	0	1061	0	0
T147	0	301	0	0
T189	0	559	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249721003	249559722	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1715	1519	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T15,T12,T37
DataWait	75	Covered	T15,T12,T37
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T15,T12,T37
DataWait->AckPls	80	Covered	T15,T12,T37
DataWait->Disabled	107	Covered	T195,T196,T162
DataWait->Error	99	Covered	T8,T174,T185
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T191,T169,T170
EndPointClear->Error	99	Covered	T4,T16,T192
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T15,T12,T37
Idle->Disabled	107	Covered	T1,T21,T10
Idle->Error	99	Covered	T5,T32,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T15,T12,T37
Idle	-	1	0	-	Covered	T15,T12,T37
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T15,T12,T37
DataWait	-	-	-	0	Covered	T15,T12,T37
AckPls	-	-	-	-	Covered	T15,T12,T37
Error	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T32
0	1	Covered	T21,T10,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	249757816	127053	0	0
FpvSecCmErrorStEscalate_A	249757816	127837	0	0
u_state_regs_A	249757816	249596535	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127053	0	0
T4	1892	1104	0	0
T5	1472	820	0	0
T6	0	1128	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	6977	0	0
T17	0	1072	0	0
T20	1768	0	0	0
T32	0	598	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	610	0	0
T64	0	1110	0	0
T147	0	350	0	0
T189	0	608	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127837	0	0
T4	1892	1105	0	0
T5	1472	821	0	0
T6	0	1129	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7107	0	0
T17	0	1073	0	0
T20	1768	0	0	0
T32	0	599	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	611	0	0
T64	0	1111	0	0
T147	0	351	0	0
T189	0	609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T15,T12
DataWait	75	Covered	T9,T15,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T15,T12
DataWait->AckPls	80	Covered	T9,T15,T12
DataWait->Disabled	107	Covered	T74,T197,T198
DataWait->Error	99	Covered	T156,T102,T199
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T191,T169,T170
EndPointClear->Error	99	Covered	T4,T16,T192
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T9,T15,T12
Idle->Disabled	107	Covered	T1,T21,T10
Idle->Error	99	Covered	T5,T32,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T9,T15,T12
Idle	-	1	0	-	Covered	T9,T15,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T9,T15,T12
DataWait	-	-	-	0	Covered	T9,T15,T12
AckPls	-	-	-	-	Covered	T9,T15,T12
Error	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T32
0	1	Covered	T21,T10,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	249757816	127053	0	0
FpvSecCmErrorStEscalate_A	249757816	127837	0	0
u_state_regs_A	249757816	249596535	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127053	0	0
T4	1892	1104	0	0
T5	1472	820	0	0
T6	0	1128	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	6977	0	0
T17	0	1072	0	0
T20	1768	0	0	0
T32	0	598	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	610	0	0
T64	0	1110	0	0
T147	0	350	0	0
T189	0	608	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127837	0	0
T4	1892	1105	0	0
T5	1472	821	0	0
T6	0	1129	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7107	0	0
T17	0	1073	0	0
T20	1768	0	0	0
T32	0	599	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	611	0	0
T64	0	1111	0	0
T147	0	351	0	0
T189	0	609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T21,T9
DataWait	75	Covered	T3,T21,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T21,T9
DataWait->AckPls	80	Covered	T3,T21,T9
DataWait->Disabled	107	Covered	T200,T201
DataWait->Error	99	Covered	T161,T121,T104
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T191,T169,T170
EndPointClear->Error	99	Covered	T4,T16,T192
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T21,T9
Idle->Disabled	107	Covered	T1,T21,T10
Idle->Error	99	Covered	T5,T32,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T21,T9
Idle	-	1	0	-	Covered	T3,T21,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T21,T9
DataWait	-	-	-	0	Covered	T3,T21,T9
AckPls	-	-	-	-	Covered	T3,T21,T9
Error	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T32
0	1	Covered	T21,T10,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	249757816	127053	0	0
FpvSecCmErrorStEscalate_A	249757816	127837	0	0
u_state_regs_A	249757816	249596535	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127053	0	0
T4	1892	1104	0	0
T5	1472	820	0	0
T6	0	1128	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	6977	0	0
T17	0	1072	0	0
T20	1768	0	0	0
T32	0	598	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	610	0	0
T64	0	1110	0	0
T147	0	350	0	0
T189	0	608	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127837	0	0
T4	1892	1105	0	0
T5	1472	821	0	0
T6	0	1129	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7107	0	0
T17	0	1073	0	0
T20	1768	0	0	0
T32	0	599	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	611	0	0
T64	0	1111	0	0
T147	0	351	0	0
T189	0	609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T15,T12
DataWait	75	Covered	T9,T15,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T15,T12
DataWait->AckPls	80	Covered	T9,T15,T12
DataWait->Disabled	107	Covered	T80,T133,T107
DataWait->Error	99	Covered	T46,T47,T184
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T191,T169,T170
EndPointClear->Error	99	Covered	T4,T16,T192
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T9,T15,T12
Idle->Disabled	107	Covered	T1,T21,T10
Idle->Error	99	Covered	T5,T32,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T9,T15,T12
Idle	-	1	0	-	Covered	T9,T15,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T9,T15,T12
DataWait	-	-	-	0	Covered	T9,T15,T12
AckPls	-	-	-	-	Covered	T9,T15,T12
Error	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T32
0	1	Covered	T21,T10,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	249757816	127053	0	0
FpvSecCmErrorStEscalate_A	249757816	127837	0	0
u_state_regs_A	249757816	249596535	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127053	0	0
T4	1892	1104	0	0
T5	1472	820	0	0
T6	0	1128	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	6977	0	0
T17	0	1072	0	0
T20	1768	0	0	0
T32	0	598	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	610	0	0
T64	0	1110	0	0
T147	0	350	0	0
T189	0	608	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127837	0	0
T4	1892	1105	0	0
T5	1472	821	0	0
T6	0	1129	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7107	0	0
T17	0	1073	0	0
T20	1768	0	0	0
T32	0	599	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	611	0	0
T64	0	1111	0	0
T147	0	351	0	0
T189	0	609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T10,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T15,T38
DataWait	75	Covered	T9,T15,T38
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T38
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T15,T38
DataWait->AckPls	80	Covered	T9,T15,T38
DataWait->Disabled	107	Covered	T190,T202,T203
DataWait->Error	99	Covered	T148,T158,T149
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T191,T169,T170
EndPointClear->Error	99	Covered	T4,T16,T192
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T9,T15,T38
Idle->Disabled	107	Covered	T1,T21,T10
Idle->Error	99	Covered	T5,T32,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T9,T15,T38
Idle	-	1	0	-	Covered	T9,T15,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T9,T15,T38
DataWait	-	-	-	0	Covered	T9,T15,T38
AckPls	-	-	-	-	Covered	T9,T15,T38
Error	-	-	-	-	Covered	T4,T5,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T32
0	1	Covered	T21,T10,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	249757816	127053	0	0
FpvSecCmErrorStEscalate_A	249757816	127837	0	0
u_state_regs_A	249757816	249596535	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127053	0	0
T4	1892	1104	0	0
T5	1472	820	0	0
T6	0	1128	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	6977	0	0
T17	0	1072	0	0
T20	1768	0	0	0
T32	0	598	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	610	0	0
T64	0	1110	0	0
T147	0	350	0	0
T189	0	608	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	127837	0	0
T4	1892	1105	0	0
T5	1472	821	0	0
T6	0	1129	0	0
T11	1867	0	0	0
T12	2216	0	0	0
T15	2220	0	0	0
T16	0	7107	0	0
T17	0	1073	0	0
T20	1768	0	0	0
T32	0	599	0	0
T38	813	0	0	0
T40	2191	0	0	0
T49	2099	0	0	0
T50	2788	0	0	0
T57	0	611	0	0
T64	0	1111	0	0
T147	0	351	0	0
T189	0	609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0