Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T33
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T31,T29
1	0	1	Covered	T9,T10,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T15

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498936434	1018804	0	0
DepthKnown_A	499515632	499193070	0	0
RvalidKnown_A	499515632	499193070	0	0
WreadyKnown_A	499515632	499193070	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	499291668	1100639	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498936434	1018804	0	0
T4	282	0	0	0
T9	9478	3432	0	0
T10	4964	334	0	0
T11	3734	2294	0	0
T12	0	1692	0	0
T15	4440	1339	0	0
T20	3536	315	0	0
T22	8206	0	0	0
T23	2008	0	0	0
T24	5776	0	0	0
T38	1626	0	0	0
T40	0	588	0	0
T41	0	847	0	0
T50	0	3405	0	0
T63	0	510	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499515632	499193070	0	0
T1	1009950	1009936	0	0
T2	2928	2826	0	0
T3	3038	2910	0	0
T4	3784	3392	0	0
T9	9478	9310	0	0
T10	4964	4786	0	0
T21	3786	3676	0	0
T22	8206	8098	0	0
T23	2008	1852	0	0
T24	5776	5660	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499515632	499193070	0	0
T1	1009950	1009936	0	0
T2	2928	2826	0	0
T3	3038	2910	0	0
T4	3784	3392	0	0
T9	9478	9310	0	0
T10	4964	4786	0	0
T21	3786	3676	0	0
T22	8206	8098	0	0
T23	2008	1852	0	0
T24	5776	5660	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499515632	499193070	0	0
T1	1009950	1009936	0	0
T2	2928	2826	0	0
T3	3038	2910	0	0
T4	3784	3392	0	0
T9	9478	9310	0	0
T10	4964	4786	0	0
T21	3786	3676	0	0
T22	8206	8098	0	0
T23	2008	1852	0	0
T24	5776	5660	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	499291668	1100639	0	0
T4	3784	272	0	0
T5	0	438	0	0
T9	9478	3432	0	0
T10	4964	334	0	0
T11	3734	2294	0	0
T12	0	1692	0	0
T15	4440	1339	0	0
T20	3536	315	0	0
T22	8206	0	0	0
T23	2008	0	0	0
T24	5776	0	0	0
T38	1626	0	0	0
T40	0	588	0	0
T50	0	3405	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T6,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T81,T82
1	0	1	Covered	T9,T10,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	249468217	503946	0	0
DepthKnown_A	249757816	249596535	0	0
RvalidKnown_A	249757816	249596535	0	0
WreadyKnown_A	249757816	249596535	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	249645834	544631	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249468217	503946	0	0
T4	141	0	0	0
T9	4739	1654	0	0
T10	2482	171	0	0
T11	1867	1088	0	0
T12	0	832	0	0
T15	2220	666	0	0
T20	1768	158	0	0
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T38	813	0	0	0
T40	0	280	0	0
T41	0	391	0	0
T50	0	1614	0	0
T63	0	254	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	249645834	544631	0	0
T4	1892	141	0	0
T5	0	220	0	0
T9	4739	1654	0	0
T10	2482	171	0	0
T11	1867	1088	0	0
T12	0	832	0	0
T15	2220	666	0	0
T20	1768	158	0	0
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T38	813	0	0	0
T40	0	280	0	0
T50	0	1614	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T31,T83
1	0	1	Covered	T9,T10,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	249468217	514858	0	0
DepthKnown_A	249757816	249596535	0	0
RvalidKnown_A	249757816	249596535	0	0
WreadyKnown_A	249757816	249596535	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	249645834	556008	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249468217	514858	0	0
T4	141	0	0	0
T9	4739	1778	0	0
T10	2482	163	0	0
T11	1867	1206	0	0
T12	0	860	0	0
T15	2220	673	0	0
T20	1768	157	0	0
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T38	813	0	0	0
T40	0	308	0	0
T41	0	456	0	0
T50	0	1791	0	0
T63	0	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	249757816	249596535	0	0
T1	504975	504968	0	0
T2	1464	1413	0	0
T3	1519	1455	0	0
T4	1892	1696	0	0
T9	4739	4655	0	0
T10	2482	2393	0	0
T21	1893	1838	0	0
T22	4103	4049	0	0
T23	1004	926	0	0
T24	2888	2830	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	249645834	556008	0	0
T4	1892	131	0	0
T5	0	218	0	0
T9	4739	1778	0	0
T10	2482	163	0	0
T11	1867	1206	0	0
T12	0	860	0	0
T15	2220	673	0	0
T20	1768	157	0	0
T22	4103	0	0	0
T23	1004	0	0	0
T24	2888	0	0	0
T38	813	0	0	0
T40	0	308	0	0
T50	0	1791	0	0