Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	641656	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5141205

1

T1

10

T2

20

T3

43

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1529593	1			T1	35		T2	100		T3	87
values[0x0]	1966684	1			T1	4		T2	14		T3	20
values[0x1]	2286584	1			T1	4		T2	4		T3	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	318514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5464347

1

T1

24

T2

40

T3

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22689	1			T3	2		T6	599		T10	1
valid_sources[0x01]	22644	1			T6	243		T50	4		T10	2
valid_sources[0x02]	21945	1			T26	1		T6	540		T42	1
valid_sources[0x03]	21594	1			T2	4		T3	1		T6	100
valid_sources[0x04]	22136	1			T6	271		T50	1		T80	1
valid_sources[0x05]	22644	1			T2	1		T6	210		T44	1
valid_sources[0x06]	23816	1			T4	4		T26	1		T6	133
valid_sources[0x07]	23450	1			T1	1		T6	764		T50	3
valid_sources[0x08]	22708	1			T3	2		T26	2		T6	361
valid_sources[0x09]	25074	1			T1	2		T6	728		T50	1
valid_sources[0x0a]	22258	1			T26	1		T6	192		T45	1
valid_sources[0x0b]	23479	1			T17	1		T6	520		T42	1
valid_sources[0x0c]	22673	1			T6	338		T50	4		T42	1
valid_sources[0x0d]	23455	1			T3	1		T26	1		T6	230
valid_sources[0x0e]	21884	1			T3	1		T4	9		T26	1
valid_sources[0x0f]	22349	1			T1	1		T3	1		T6	237
valid_sources[0x10]	22344	1			T3	2		T6	77		T50	2
valid_sources[0x11]	22553	1			T26	1		T6	284		T50	2
valid_sources[0x12]	21581	1			T2	3		T3	1		T6	213
valid_sources[0x13]	22026	1			T17	1		T6	201		T30	1
valid_sources[0x14]	22398	1			T6	540		T50	2		T44	2
valid_sources[0x15]	21218	1			T17	1		T6	622		T50	2
valid_sources[0x16]	23121	1			T2	1		T6	606		T45	2
valid_sources[0x17]	23469	1			T3	1		T6	618		T50	1
valid_sources[0x18]	23248	1			T17	3		T5	24		T26	1
valid_sources[0x19]	21648	1			T2	3		T6	287		T50	3
valid_sources[0x1a]	21217	1			T6	296		T50	1		T44	2
valid_sources[0x1b]	22817	1			T1	1		T3	1		T4	17
valid_sources[0x1c]	22068	1			T6	560		T34	2		T44	1
valid_sources[0x1d]	21363	1			T2	3		T6	224		T50	1
valid_sources[0x1e]	20709	1			T3	1		T17	1		T6	53
valid_sources[0x1f]	21158	1			T6	32		T50	1		T44	1
valid_sources[0x20]	23442	1			T3	2		T6	288		T10	1
valid_sources[0x21]	23144	1			T26	2		T6	69		T10	1
valid_sources[0x22]	22950	1			T1	1		T17	1		T4	44
valid_sources[0x23]	21185	1			T3	2		T4	25		T26	1
valid_sources[0x24]	22019	1			T1	1		T26	1		T6	278
valid_sources[0x25]	23708	1			T6	34		T44	1		T43	1
valid_sources[0x26]	21055	1			T3	2		T4	37		T6	354
valid_sources[0x27]	23094	1			T6	192		T50	1		T14	3
valid_sources[0x28]	21955	1			T6	514		T50	6		T10	4
valid_sources[0x29]	22305	1			T1	1		T17	1		T6	284
valid_sources[0x2a]	20682	1			T3	1		T6	516		T50	5
valid_sources[0x2b]	24290	1			T1	3		T3	1		T26	1
valid_sources[0x2c]	22329	1			T3	1		T4	70		T6	163
valid_sources[0x2d]	23757	1			T17	2		T6	345		T50	10
valid_sources[0x2e]	22654	1			T4	1		T26	1		T6	356
valid_sources[0x2f]	21867	1			T6	451		T50	1		T44	2
valid_sources[0x30]	23026	1			T3	1		T4	2		T26	2
valid_sources[0x31]	21105	1			T6	709		T42	1		T14	4
valid_sources[0x32]	22053	1			T17	2		T6	150		T50	1
valid_sources[0x33]	22283	1			T3	1		T6	659		T42	2
valid_sources[0x34]	23363	1			T3	1		T17	1		T4	24
valid_sources[0x35]	22043	1			T17	1		T6	138		T50	4
valid_sources[0x36]	22749	1			T3	1		T17	3		T6	150
valid_sources[0x37]	23430	1			T1	1		T2	2		T17	1
valid_sources[0x38]	21303	1			T2	1		T3	1		T17	3
valid_sources[0x39]	21783	1			T3	3		T17	1		T4	14
valid_sources[0x3a]	21963	1			T2	3		T6	215		T50	2
valid_sources[0x3b]	21506	1			T3	2		T5	15		T6	511
valid_sources[0x3c]	24567	1			T2	3		T6	359		T50	2
valid_sources[0x3d]	22971	1			T3	1		T6	275		T10	1
valid_sources[0x3e]	22181	1			T6	272		T50	1		T42	1
valid_sources[0x3f]	25975	1			T1	1		T3	1		T6	766
valid_sources[0x40]	23347	1			T3	1		T6	70		T50	4
valid_sources[0x41]	21711	1			T3	1		T17	2		T26	1
valid_sources[0x42]	23100	1			T3	1		T17	1		T26	6
valid_sources[0x43]	23994	1			T2	1		T3	1		T6	369
valid_sources[0x44]	21929	1			T2	3		T6	392		T34	1
valid_sources[0x45]	20792	1			T6	413		T50	1		T42	1
valid_sources[0x46]	23011	1			T26	1		T6	980		T10	1
valid_sources[0x47]	22937	1			T1	1		T6	196		T50	1
valid_sources[0x48]	21211	1			T6	591		T50	2		T42	1
valid_sources[0x49]	22861	1			T6	348		T50	3		T43	1
valid_sources[0x4a]	22856	1			T6	576		T50	2		T44	4
valid_sources[0x4b]	21419	1			T4	7		T6	138		T50	1
valid_sources[0x4c]	21913	1			T17	1		T6	381		T42	2
valid_sources[0x4d]	22780	1			T17	1		T6	534		T50	3
valid_sources[0x4e]	21453	1			T3	2		T6	610		T50	1
valid_sources[0x4f]	23218	1			T6	317		T44	1		T92	2
valid_sources[0x50]	23264	1			T2	9		T6	623		T50	1
valid_sources[0x51]	23274	1			T1	1		T17	1		T6	475
valid_sources[0x52]	22719	1			T6	280		T50	2		T43	1
valid_sources[0x53]	21620	1			T3	2		T17	1		T6	388
valid_sources[0x54]	22238	1			T3	1		T17	1		T6	608
valid_sources[0x55]	21828	1			T3	1		T6	543		T50	1
valid_sources[0x56]	23156	1			T1	1		T3	1		T17	2
valid_sources[0x57]	23581	1			T2	4		T3	1		T17	1
valid_sources[0x58]	24072	1			T2	1		T3	1		T17	1
valid_sources[0x59]	25466	1			T1	1		T3	2		T6	759
valid_sources[0x5a]	23860	1			T1	1		T6	536		T50	1
valid_sources[0x5b]	21671	1			T6	147		T42	1		T14	1
valid_sources[0x5c]	22099	1			T26	2		T6	555		T44	3
valid_sources[0x5d]	22698	1			T17	1		T6	268		T50	2
valid_sources[0x5e]	21908	1			T3	1		T6	388		T50	1
valid_sources[0x5f]	21914	1			T3	2		T6	284		T42	1
valid_sources[0x60]	23300	1			T6	597		T42	1		T14	1
valid_sources[0x61]	23726	1			T3	1		T26	1		T6	380
valid_sources[0x62]	22231	1			T26	1		T6	292		T80	1
valid_sources[0x63]	22236	1			T4	5		T6	251		T50	1
valid_sources[0x64]	21883	1			T1	1		T3	1		T17	2
valid_sources[0x65]	22640	1			T2	14		T3	1		T4	19
valid_sources[0x66]	23439	1			T26	1		T6	661		T50	1
valid_sources[0x67]	21661	1			T3	1		T6	531		T80	1
valid_sources[0x68]	23275	1			T6	235		T50	1		T10	3
valid_sources[0x69]	22607	1			T6	65		T50	1		T10	1
valid_sources[0x6a]	25949	1			T3	3		T6	992		T50	2
valid_sources[0x6b]	22118	1			T6	523		T42	2		T10	1
valid_sources[0x6c]	22164	1			T2	1		T6	221		T50	8
valid_sources[0x6d]	21856	1			T6	934		T10	1		T44	1
valid_sources[0x6e]	22862	1			T2	1		T17	1		T6	236
valid_sources[0x6f]	22689	1			T2	3		T17	1		T26	1
valid_sources[0x70]	23429	1			T6	223		T14	1		T43	3
valid_sources[0x71]	21748	1			T2	1		T17	1		T26	1
valid_sources[0x72]	24245	1			T17	2		T6	870		T14	1
valid_sources[0x73]	22007	1			T2	1		T6	358		T44	1
valid_sources[0x74]	23801	1			T2	2		T17	1		T6	339
valid_sources[0x75]	22374	1			T6	363		T42	2		T44	2
valid_sources[0x76]	23912	1			T1	2		T6	688		T50	3
valid_sources[0x77]	22471	1			T1	1		T6	651		T50	1
valid_sources[0x78]	22727	1			T17	1		T6	71		T10	1
valid_sources[0x79]	21997	1			T26	1		T6	477		T42	2
valid_sources[0x7a]	22292	1			T6	489		T50	3		T10	2
valid_sources[0x7b]	23395	1			T2	8		T3	1		T17	1
valid_sources[0x7c]	22068	1			T26	1		T6	685		T50	2
valid_sources[0x7d]	23441	1			T3	1		T4	68		T6	44
valid_sources[0x7e]	24544	1			T6	635		T50	1		T42	1
valid_sources[0x7f]	22200	1			T6	609		T10	2		T14	4
valid_sources[0x80]	22755	1			T3	1		T6	434		T50	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1294519

1

T1

4

T2

6

T3

6

values[0x0]

all_enables

biggest_size

1924755

1

T1

2

T2

11

T3

16

values[0x1]

all_enables

biggest_size

1921931

1

T1

4

T2

3

T3

21