Summary for Variable csrng_clen_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for csrng_clen_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
non_zero_bins[0] |
2569 |
1 |
|
|
T2 |
2 |
|
T9 |
2 |
|
T4 |
7 |
non_zero_bins[1] |
1972 |
1 |
|
|
T3 |
3 |
|
T4 |
9 |
|
T6 |
31 |
zero |
9626 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T3 |
2 |
Summary for Variable csrng_cmd_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for csrng_cmd_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
upd |
505 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
9 |
uni |
3807 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
2 |
gen |
4485 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
res |
804 |
1 |
|
|
T9 |
2 |
|
T4 |
1 |
|
T6 |
11 |
ins |
4566 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
2 |
Summary for Variable csrng_flag_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_flag_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
mubi_false |
9377 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
3 |
mubi_true |
4790 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
2 |
Summary for Variable csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_sts
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
fail |
19 |
1 |
|
|
T14 |
1 |
|
T49 |
1 |
|
T94 |
1 |
pass |
14148 |
1 |
|
|
T1 |
3 |
|
T2 |
7 |
|
T3 |
5 |
Summary for Cross csrng_cmd_cross
Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
52 |
24 |
28 |
53.85 |
24 |
Automatically Generated Cross Bins |
52 |
24 |
28 |
53.85 |
24 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for csrng_cmd_cross
Element holes
csrng_cmd_cp | csrng_clen_cp | csrng_sts | csrng_flag_cp | COUNT | AT LEAST | NUMBER | STATUS |
[upd] |
* |
[fail] |
* |
-- |
-- |
6 |
|
[uni] |
[zero] |
[fail] |
* |
-- |
-- |
2 |
|
[gen , res] |
[non_zero_bins[0] , non_zero_bins[1]] |
[fail] |
* |
-- |
-- |
8 |
|
[ins] |
* |
[fail] |
* |
-- |
-- |
6 |
|
Uncovered bins
csrng_cmd_cp | csrng_clen_cp | csrng_sts | csrng_flag_cp | COUNT | AT LEAST | NUMBER | STATUS |
[gen , res] |
[zero] |
[fail] |
[mubi_true] |
-- |
-- |
2 |
|
Covered bins
csrng_cmd_cp | csrng_clen_cp | csrng_sts | csrng_flag_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
upd |
non_zero_bins[0] |
pass |
mubi_false |
123 |
1 |
|
|
T4 |
1 |
|
T6 |
5 |
|
T279 |
1 |
upd |
non_zero_bins[0] |
pass |
mubi_true |
107 |
1 |
|
|
T6 |
1 |
|
T40 |
2 |
|
T41 |
1 |
upd |
non_zero_bins[1] |
pass |
mubi_false |
89 |
1 |
|
|
T6 |
1 |
|
T40 |
2 |
|
T41 |
2 |
upd |
non_zero_bins[1] |
pass |
mubi_true |
83 |
1 |
|
|
T6 |
1 |
|
T40 |
1 |
|
T41 |
2 |
upd |
zero |
pass |
mubi_false |
55 |
1 |
|
|
T40 |
1 |
|
T46 |
1 |
|
T86 |
1 |
upd |
zero |
pass |
mubi_true |
48 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T77 |
2 |
uni |
zero |
pass |
mubi_false |
2779 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T9 |
1 |
uni |
zero |
pass |
mubi_true |
1028 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
7 |
gen |
non_zero_bins[0] |
pass |
mubi_false |
554 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T6 |
7 |
gen |
non_zero_bins[0] |
pass |
mubi_true |
461 |
1 |
|
|
T9 |
1 |
|
T4 |
1 |
|
T6 |
6 |
gen |
non_zero_bins[1] |
pass |
mubi_false |
298 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T6 |
3 |
gen |
non_zero_bins[1] |
pass |
mubi_true |
399 |
1 |
|
|
T6 |
8 |
|
T279 |
1 |
|
T22 |
11 |
gen |
zero |
fail |
mubi_false |
15 |
1 |
|
|
T14 |
1 |
|
T49 |
1 |
|
T280 |
1 |
gen |
zero |
pass |
mubi_false |
1982 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T9 |
3 |
gen |
zero |
pass |
mubi_true |
776 |
1 |
|
|
T17 |
2 |
|
T26 |
2 |
|
T6 |
2 |
res |
non_zero_bins[0] |
pass |
mubi_false |
148 |
1 |
|
|
T6 |
1 |
|
T41 |
3 |
|
T77 |
1 |
res |
non_zero_bins[0] |
pass |
mubi_true |
194 |
1 |
|
|
T6 |
2 |
|
T50 |
1 |
|
T45 |
1 |
res |
non_zero_bins[1] |
pass |
mubi_false |
156 |
1 |
|
|
T4 |
1 |
|
T6 |
2 |
|
T44 |
1 |
res |
non_zero_bins[1] |
pass |
mubi_true |
128 |
1 |
|
|
T6 |
2 |
|
T281 |
1 |
|
T40 |
2 |
res |
zero |
fail |
mubi_false |
4 |
1 |
|
|
T94 |
1 |
|
T158 |
1 |
|
T282 |
1 |
res |
zero |
pass |
mubi_false |
121 |
1 |
|
|
T6 |
3 |
|
T10 |
2 |
|
T43 |
1 |
res |
zero |
pass |
mubi_true |
53 |
1 |
|
|
T9 |
2 |
|
T6 |
1 |
|
T40 |
1 |
ins |
non_zero_bins[0] |
pass |
mubi_false |
490 |
1 |
|
|
T4 |
1 |
|
T6 |
6 |
|
T50 |
1 |
ins |
non_zero_bins[0] |
pass |
mubi_true |
492 |
1 |
|
|
T2 |
1 |
|
T9 |
1 |
|
T4 |
2 |
ins |
non_zero_bins[1] |
pass |
mubi_false |
421 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T6 |
5 |
ins |
non_zero_bins[1] |
pass |
mubi_true |
398 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T6 |
9 |
ins |
zero |
pass |
mubi_false |
2142 |
1 |
|
|
T1 |
1 |
|
T17 |
1 |
|
T4 |
5 |
ins |
zero |
pass |
mubi_true |
623 |
1 |
|
|
T2 |
1 |
|
T17 |
1 |
|
T25 |
1 |
User Defined Cross Bins for csrng_cmd_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
uni_clen |
0 |
Excluded |