Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T17,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T17,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T38
1	1	0	Not Covered
1	1	1	Covered	T9,T17,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T33,T39
1	0	1	Covered	T9,T17,T5
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T17,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423028148	948961	0	0
DepthKnown_A	423915352	423538102	0	0
RvalidKnown_A	423915352	423538102	0	0
WreadyKnown_A	423915352	423538102	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	423366966	1032571	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423028148	948961	0	0
T4	65670	0	0	0
T5	702	337	0	0
T6	913004	0	0	0
T7	0	324	0	0
T9	9994	6233	0	0
T10	0	2384	0	0
T14	0	887	0	0
T17	4030	311	0	0
T21	0	3396	0	0
T22	0	2040	0	0
T25	2592	0	0	0
T26	3918	0	0	0
T42	4394	0	0	0
T49	0	218	0	0
T50	36032	0	0	0
T79	1838	0	0	0
T97	0	412	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423915352	423538102	0	0
T1	2036	1900	0	0
T2	5164	5030	0	0
T3	5462	5292	0	0
T4	65670	64210	0	0
T5	2368	2052	0	0
T6	913004	912974	0	0
T9	9994	9866	0	0
T17	4030	3920	0	0
T25	2592	2392	0	0
T26	3918	3780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423915352	423538102	0	0
T1	2036	1900	0	0
T2	5164	5030	0	0
T3	5462	5292	0	0
T4	65670	64210	0	0
T5	2368	2052	0	0
T6	913004	912974	0	0
T9	9994	9866	0	0
T17	4030	3920	0	0
T25	2592	2392	0	0
T26	3918	3780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423915352	423538102	0	0
T1	2036	1900	0	0
T2	5164	5030	0	0
T3	5462	5292	0	0
T4	65670	64210	0	0
T5	2368	2052	0	0
T6	913004	912974	0	0
T9	9994	9866	0	0
T17	4030	3920	0	0
T25	2592	2392	0	0
T26	3918	3780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	423366966	1032571	0	0
T4	65670	0	0	0
T5	2368	1299	0	0
T6	913004	0	0	0
T7	0	1402	0	0
T9	9994	6233	0	0
T10	0	2384	0	0
T14	0	887	0	0
T17	4030	311	0	0
T21	0	3396	0	0
T22	0	2040	0	0
T25	2592	0	0	0
T26	3918	0	0	0
T42	4394	0	0	0
T49	0	218	0	0
T50	36032	0	0	0
T79	1838	0	0	0
T97	0	412	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T31,T85
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T17,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31
1	1	0	Not Covered
1	1	1	Covered	T9,T17,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T33,T98
1	0	1	Covered	T9,T17,T5
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T17,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	211514074	469060	0	0
DepthKnown_A	211957676	211769051	0	0
RvalidKnown_A	211957676	211769051	0	0
WreadyKnown_A	211957676	211769051	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	211683483	510612	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211514074	469060	0	0
T4	32835	0	0	0
T5	351	126	0	0
T6	456502	0	0	0
T7	0	120	0	0
T9	4997	3047	0	0
T10	0	1178	0	0
T14	0	441	0	0
T17	2015	155	0	0
T21	0	1696	0	0
T22	0	993	0	0
T25	1296	0	0	0
T26	1959	0	0	0
T42	2197	0	0	0
T49	0	59	0	0
T50	18016	0	0	0
T79	919	0	0	0
T97	0	207	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	211683483	510612	0	0
T4	32835	0	0	0
T5	1184	583	0	0
T6	456502	0	0	0
T7	0	621	0	0
T9	4997	3047	0	0
T10	0	1178	0	0
T14	0	441	0	0
T17	2015	155	0	0
T21	0	1696	0	0
T22	0	993	0	0
T25	1296	0	0	0
T26	1959	0	0	0
T42	2197	0	0	0
T49	0	59	0	0
T50	18016	0	0	0
T79	919	0	0	0
T97	0	207	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T17,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T17,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38
1	1	0	Not Covered
1	1	1	Covered	T9,T17,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39
1	0	1	Covered	T9,T17,T5
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T17,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	211514074	479901	0	0
DepthKnown_A	211957676	211769051	0	0
RvalidKnown_A	211957676	211769051	0	0
WreadyKnown_A	211957676	211769051	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	211683483	521959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211514074	479901	0	0
T4	32835	0	0	0
T5	351	211	0	0
T6	456502	0	0	0
T7	0	204	0	0
T9	4997	3186	0	0
T10	0	1206	0	0
T14	0	446	0	0
T17	2015	156	0	0
T21	0	1700	0	0
T22	0	1047	0	0
T25	1296	0	0	0
T26	1959	0	0	0
T42	2197	0	0	0
T49	0	159	0	0
T50	18016	0	0	0
T79	919	0	0	0
T97	0	205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	211683483	521959	0	0
T4	32835	0	0	0
T5	1184	716	0	0
T6	456502	0	0	0
T7	0	781	0	0
T9	4997	3186	0	0
T10	0	1206	0	0
T14	0	446	0	0
T17	2015	156	0	0
T21	0	1700	0	0
T22	0	1047	0	0
T25	1296	0	0	0
T26	1959	0	0	0
T42	2197	0	0	0
T49	0	159	0	0
T50	18016	0	0	0
T79	919	0	0	0
T97	0	205	0	0