Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	141	1			T3	1		T24	1		T45	1
auto_req_mode	151	1			T11	1		T20	1		T21	1
sw_mode	2788	1			T26	1		T66	1		T5	3

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

308

1

T3

1

T24

1

T11

1

single

92

1

T45

1

T251

1

T47

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1240	1			T3	1		T26	1		T66	1
auto[2]	82	1			T49	1		T111	11		T319	1
auto[3]	249	1			T11	1		T13	1		T116	1
auto[4]	116	1			T84	1		T40	31		T51	1
auto[5]	94	1			T45	1		T320	1		T321	1
auto[6]	128	1			T55	1		T322	1		T69	1
auto[7]	1171	1			T24	1		T47	1		T48	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	81	1			T3	1		T117	1		T93	1
auto[1]	auto_req_mode	84	1			T20	1		T21	1		T323	1
auto[1]	sw_mode	1075	1			T26	1		T66	1		T5	3
auto[2]	boot_req_mode	2	1			T288	1		T324	1		-	-
auto[2]	auto_req_mode	4	1			T325	1		T326	1		T327	1
auto[2]	sw_mode	76	1			T49	1		T111	11		T319	1
auto[3]	boot_req_mode	4	1			T328	1		T329	1		T330	1
auto[3]	auto_req_mode	5	1			T11	1		T13	1		T331	1
auto[3]	sw_mode	240	1			T116	1		T82	31		T332	60
auto[4]	boot_req_mode	8	1			T287	1		T333	1		T334	1
auto[4]	auto_req_mode	7	1			T51	1		T88	1		T335	1
auto[4]	sw_mode	101	1			T84	1		T40	31		T110	1
auto[5]	boot_req_mode	4	1			T45	1		T320	1		T336	1
auto[5]	auto_req_mode	3	1			T321	1		T337	1		T338	1
auto[5]	sw_mode	87	1			T339	3		T76	1		T340	21
auto[6]	boot_req_mode	5	1			T55	1		T322	1		T69	1
auto[6]	auto_req_mode	2	1			T341	1		T342	1		-	-
auto[6]	sw_mode	121	1			T244	45		T343	1		T344	13
auto[7]	boot_req_mode	37	1			T24	1		T48	1		T52	1
auto[7]	auto_req_mode	46	1			T12	1		T97	1		T54	1
auto[7]	sw_mode	1088	1			T47	1		T53	1		T41	51