Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cs_cmds_cg

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cs_cmds_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cs_cmds_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cs_cmds_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	34	0	34	100.00

Variables for Group Instance edn_cs_cmds_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acmd	5	0	5	100.00	100	1	1	0
cp_clen	2	0	2	100.00	100	1	1	0
cp_cmd_src	5	0	5	100.00	100	1	1	0
cp_flags	2	0	2	100.00	100	1	1	0
cp_glen	2	0	2	100.00	100	1	1	0
cp_mode	3	0	3	100.00	100	1	1	0

Crosses for Group Instance edn_cs_cmds_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_generate_intended	9	0	9	100.00	100	1	1	0
cr_instantiate_intended	9	0	9	100.00	100	1	1	0
cr_reseed_intended	8	0	8	100.00	100	1	1	0
cr_update_intended	2	0	2	100.00	100	1	1	0
cr_uninstantiate_intended	1	0	1	100.00	100	1	1	0
cr_acmd_mode_cmd_src_unintended	5	0	5	100.00	100	1	1	0

Summary for Variable cp_acmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_acmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[INV]	0	Excluded
auto[GENB]	0	Excluded
auto[GENU]	0	Excluded
unused	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[INS]	4289	1			T1	2		T2	1		T3	2
auto[RES]	1122	1			T1	1		T10	1		T11	1
auto[GEN]	4396	1			T1	3		T2	3		T3	2
auto[UPD]	508	1			T3	1		T24	1		T20	1
auto[UNI]	3481	1			T3	1		T24	1		T26	1

---

Summary for Variable cp_clen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_clen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

some_cmd_data

4432

1

T3

3

T24

3

T11

5

no_cmd_data

9368

1

T1

6

T2

4

T3

3

---

Summary for Variable cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_cmd_src

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_cmd_req	11965	1			T1	4		T2	3		T3	4
reseed_cmd	576	1			T1	1		T10	1		T11	1
generate_cmd	544	1			T1	1		T10	1		T11	1
boot_gen_cmd	400	1			T2	1		T3	1		T23	2
boot_ins_cmd	315	1			T3	1		T23	1		T24	1

---

Summary for Variable cp_flags

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_flags

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

true

4587

1

T1

3

T2

3

T23

4

false

9213

1

T1

3

T2

1

T3

6

---

Summary for Variable cp_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_glen

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

1425

1

T3

2

T23

1

T24

4

one

2586

1

T1

3

T2

3

T3

2

---

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_mode	10962	1			T3	4		T24	4		T26	3
boot_mode	815	1			T2	1		T3	2		T23	3
auto_mode	2023	1			T1	6		T2	3		T23	3

---

Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	9	0	9	100.00
Automatically Generated Cross Bins	9	0	9	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_glen	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[multiple , one]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[multiple , one]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_glen

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[GEN]

some_cmd_data

multiple

sw_mode

sw_cmd_req

187

1

T24

1

T45

1

T251

1

auto[GEN]

some_cmd_data

multiple

auto_mode

generate_cmd

128

1

T11

1

T15

1

T20

1

auto[GEN]

some_cmd_data

one

sw_mode

sw_cmd_req

56

1

T3

1

T11

1

T20

1

auto[GEN]

some_cmd_data

one

auto_mode

generate_cmd

139

1

T21

2

T12

1

T13

1

auto[GEN]

no_cmd_data

multiple

sw_mode

sw_cmd_req

44

1

T117

1

T114

1

T345

1

auto[GEN]

no_cmd_data

multiple

boot_mode

boot_gen_cmd

63

1

T3

1

T24

1

T117

1

auto[GEN]

no_cmd_data

multiple

auto_mode

generate_cmd

35

1

T346

1

T169

1

T8

1

auto[GEN]

no_cmd_data

one

sw_mode

sw_cmd_req

1443

1

T26

1

T4

1

T66

1

auto[GEN]

no_cmd_data

one

auto_mode

generate_cmd

174

1

T1

1

T10

1

T58

1

User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_gen	0	Excluded
gen_auto_wrong_src	0	Excluded
gen_boot_wrong_src	0	Excluded
gen_boot_seq_wrong_clen	0	Excluded
gen_boot_seq_wrong_glen	0	Excluded
gen_sw_wrong_src	0	Excluded

---

Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	9	0	9	100.00
Automatically Generated Cross Bins	9	0	9	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_flags

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

some_cmd_data

true

sw_mode

sw_cmd_req

796

1

T5

2

T251

1

T49

1

auto[INS]

some_cmd_data

true

auto_mode

sw_cmd_req

85

1

T20

1

T21

2

T12

1

auto[INS]

some_cmd_data

false

sw_mode

sw_cmd_req

771

1

T3

1

T24

1

T45

1

auto[INS]

some_cmd_data

false

auto_mode

sw_cmd_req

86

1

T11

2

T13

1

T88

1

auto[INS]

no_cmd_data

true

sw_mode

sw_cmd_req

203

1

T5

1

T117

1

T40

1

auto[INS]

no_cmd_data

true

auto_mode

sw_cmd_req

222

1

T1

1

T2

1

T23

1

auto[INS]

no_cmd_data

false

sw_mode

sw_cmd_req

1652

1

T26

1

T4

1

T66

1

auto[INS]

no_cmd_data

false

boot_mode

boot_ins_cmd

162

1

T3

1

T23

1

T58

1

auto[INS]

no_cmd_data

false

auto_mode

sw_cmd_req

159

1

T1

1

T10

1

T58

1

User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_ins	0	Excluded
ins_auto_wrong_src	0	Excluded
ins_boot_wrong_src	0	Excluded
ins_boot_seq_wrong_clen	0	Excluded
ins_boot_seq_wrong_flag0	0	Excluded
ins_sw_wrong_src	0	Excluded

---

Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_flags

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[RES]

some_cmd_data

true

sw_mode

sw_cmd_req

207

1

T40

4

T41

2

T111

3

auto[RES]

some_cmd_data

true

auto_mode

reseed_cmd

130

1

T20

1

T21

1

T12

1

auto[RES]

some_cmd_data

false

sw_mode

sw_cmd_req

204

1

T47

1

T114

1

T40

1

auto[RES]

some_cmd_data

false

auto_mode

reseed_cmd

138

1

T11

1

T15

1

T21

1

auto[RES]

no_cmd_data

true

sw_mode

sw_cmd_req

58

1

T40

1

T41

1

T42

2

auto[RES]

no_cmd_data

true

auto_mode

reseed_cmd

29

1

T164

1

T162

1

T183

1

auto[RES]

no_cmd_data

false

sw_mode

sw_cmd_req

52

1

T5

1

T52

1

T40

1

auto[RES]

no_cmd_data

false

auto_mode

reseed_cmd

211

1

T1

1

T10

1

T58

1

User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_res	0	Excluded
res_auto_wrong_src	0	Excluded
res_boot_wrong_src	0	Excluded
res_sw_wrong_src	0	Excluded

---

Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)

Covered bins

cp_acmd

cp_clen

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UPD]

some_cmd_data

sw_mode

sw_cmd_req

385

1

T3

1

T24

1

T45

1

auto[UPD]

no_cmd_data

sw_mode

sw_cmd_req

106

1

T84

1

T40

2

T41

1

User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_upd	0	Excluded
upd_auto_wrong_src	0	Excluded
upd_boot_wrong_src	0	Excluded
upd_sw_wrong_src	0	Excluded

---

Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	1	0	1	100.00
Automatically Generated Cross Bins	1	0	1	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(15 bins)
[auto[GENB] , auto[GENU]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)

Covered bins

cp_acmd

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UNI]

sw_mode

sw_cmd_req

3464

1

T3

1

T24

1

T26

1

User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_uni	0	Excluded
uni_auto_wrong_src	0	Excluded
uni_boot_wrong_src	0	Excluded
uni_sw_wrong_src	0	Excluded

---

Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	0	5	100.00
Automatically Generated Cross Bins	5	0	5	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(15 bins)
[auto[GENB] , auto[GENU]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)

Covered bins

cp_acmd

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

auto_mode

sw_cmd_req

552

1

T1

2

T2

1

T23

1

auto[RES]

auto_mode

sw_cmd_req

25

1

T12

1

T51

1

T54

1

auto[GEN]

auto_mode

sw_cmd_req

424

1

T1

2

T2

2

T23

2

auto[UPD]

auto_mode

sw_cmd_req

17

1

T20

1

T13

1

T323

1

auto[UNI]

auto_mode

sw_cmd_req

17

1

T73

1

T347

1

T348

1

User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_sw_cmd	0	Excluded
not_auto_mode	0	Excluded