Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	669603	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5510914

1

T1

22

T2

16

T3

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1628260	1			T1	34		T2	27		T3	118
values[0x0]	2107231	1			T1	16		T2	13		T3	9
values[0x1]	2445026	1			T1	10		T2	10		T3	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	330347	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5850170

1

T1

29

T2

22

T3

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24853	1			T5	1		T117	1		T12	1
valid_sources[0x01]	26164	1			T23	1		T21	1		T300	1
valid_sources[0x02]	23680	1			T5	1		T84	1		T85	2
valid_sources[0x03]	23229	1			T3	2		T20	7		T21	1
valid_sources[0x04]	24356	1			T24	1		T25	1		T5	3
valid_sources[0x05]	23936	1			T5	1		T94	1		T44	11
valid_sources[0x06]	25584	1			T24	1		T25	2		T21	1
valid_sources[0x07]	25963	1			T24	3		T15	1		T5	1
valid_sources[0x08]	24664	1			T3	1		T24	5		T5	1
valid_sources[0x09]	22356	1			T5	1		T21	2		T117	1
valid_sources[0x0a]	25061	1			T3	3		T5	1		T40	205
valid_sources[0x0b]	23196	1			T3	2		T5	2		T6	1
valid_sources[0x0c]	23965	1			T5	3		T21	2		T47	2
valid_sources[0x0d]	23919	1			T21	1		T114	3		T84	1
valid_sources[0x0e]	26388	1			T117	2		T114	1		T84	1
valid_sources[0x0f]	23410	1			T3	5		T117	3		T49	2
valid_sources[0x10]	23422	1			T24	1		T65	1		T5	1
valid_sources[0x11]	24828	1			T5	3		T21	3		T117	1
valid_sources[0x12]	24042	1			T24	1		T21	1		T44	2
valid_sources[0x13]	24471	1			T2	1		T3	1		T10	1
valid_sources[0x14]	23732	1			T2	1		T65	1		T5	2
valid_sources[0x15]	22490	1			T5	1		T21	2		T117	1
valid_sources[0x16]	23164	1			T3	1		T24	1		T21	1
valid_sources[0x17]	24479	1			T23	3		T10	1		T49	1
valid_sources[0x18]	24030	1			T2	1		T5	2		T117	1
valid_sources[0x19]	24190	1			T3	1		T10	2		T5	3
valid_sources[0x1a]	21182	1			T23	2		T5	1		T21	1
valid_sources[0x1b]	24262	1			T15	2		T5	2		T47	5
valid_sources[0x1c]	24327	1			T3	1		T5	2		T21	1
valid_sources[0x1d]	24463	1			T58	2		T20	1		T44	1
valid_sources[0x1e]	25052	1			T3	2		T24	1		T5	2
valid_sources[0x1f]	25699	1			T2	1		T3	1		T10	4
valid_sources[0x20]	24106	1			T48	7		T49	1		T12	4
valid_sources[0x21]	24844	1			T15	2		T5	1		T33	1
valid_sources[0x22]	22830	1			T24	1		T5	1		T21	1
valid_sources[0x23]	23600	1			T15	1		T5	1		T20	1
valid_sources[0x24]	25035	1			T3	5		T23	1		T5	1
valid_sources[0x25]	24128	1			T3	1		T10	1		T5	3
valid_sources[0x26]	23842	1			T24	2		T25	2		T5	4
valid_sources[0x27]	24353	1			T58	7		T5	1		T44	2
valid_sources[0x28]	24010	1			T24	1		T21	1		T33	3
valid_sources[0x29]	24258	1			T24	1		T58	48		T15	1
valid_sources[0x2a]	24417	1			T2	1		T23	8		T20	6
valid_sources[0x2b]	25494	1			T24	1		T5	1		T48	1
valid_sources[0x2c]	23946	1			T3	2		T5	1		T21	1
valid_sources[0x2d]	23469	1			T23	4		T24	5		T5	1
valid_sources[0x2e]	23336	1			T24	1		T10	1		T5	1
valid_sources[0x2f]	22705	1			T24	1		T5	2		T46	1
valid_sources[0x30]	25005	1			T2	1		T5	6		T300	1
valid_sources[0x31]	23470	1			T2	1		T5	1		T21	1
valid_sources[0x32]	22836	1			T23	1		T10	1		T15	3
valid_sources[0x33]	22788	1			T5	1		T117	2		T114	1
valid_sources[0x34]	24187	1			T25	3		T94	1		T33	1
valid_sources[0x35]	22212	1			T21	1		T47	2		T13	4
valid_sources[0x36]	23178	1			T10	8		T5	3		T21	1
valid_sources[0x37]	24024	1			T5	1		T13	1		T40	115
valid_sources[0x38]	24070	1			T15	1		T5	1		T21	1
valid_sources[0x39]	24978	1			T24	1		T5	1		T117	1
valid_sources[0x3a]	24199	1			T2	1		T5	1		T49	1
valid_sources[0x3b]	24689	1			T3	1		T23	1		T24	1
valid_sources[0x3c]	25276	1			T5	1		T13	1		T40	125
valid_sources[0x3d]	23174	1			T3	1		T10	4		T15	1
valid_sources[0x3e]	23295	1			T15	1		T5	2		T21	1
valid_sources[0x3f]	24178	1			T15	1		T5	2		T46	2
valid_sources[0x40]	23634	1			T2	1		T3	4		T24	1
valid_sources[0x41]	24544	1			T2	1		T23	2		T24	1
valid_sources[0x42]	24021	1			T21	1		T117	3		T47	4
valid_sources[0x43]	24859	1			T24	1		T5	1		T49	1
valid_sources[0x44]	22905	1			T23	1		T5	3		T94	1
valid_sources[0x45]	22296	1			T114	1		T13	3		T40	152
valid_sources[0x46]	23595	1			T24	2		T46	14		T44	5
valid_sources[0x47]	25237	1			T5	1		T117	2		T114	1
valid_sources[0x48]	24081	1			T3	1		T24	2		T58	1
valid_sources[0x49]	25056	1			T117	1		T114	4		T85	1
valid_sources[0x4a]	22847	1			T65	1		T5	1		T12	1
valid_sources[0x4b]	25754	1			T24	1		T5	1		T6	2
valid_sources[0x4c]	23745	1			T24	1		T26	7		T5	1
valid_sources[0x4d]	24044	1			T3	1		T23	1		T21	3
valid_sources[0x4e]	23803	1			T5	3		T49	2		T114	1
valid_sources[0x4f]	24850	1			T3	1		T5	2		T40	120
valid_sources[0x50]	24336	1			T3	4		T5	3		T21	1
valid_sources[0x51]	23237	1			T24	1		T25	1		T15	1
valid_sources[0x52]	24350	1			T21	1		T52	2		T49	2
valid_sources[0x53]	25033	1			T5	1		T21	2		T13	1
valid_sources[0x54]	24974	1			T5	1		T21	2		T117	1
valid_sources[0x55]	23172	1			T10	1		T5	3		T20	5
valid_sources[0x56]	22359	1			T117	1		T40	126		T53	2
valid_sources[0x57]	25503	1			T2	1		T3	2		T24	2
valid_sources[0x58]	23007	1			T3	1		T24	3		T5	2
valid_sources[0x59]	22346	1			T5	4		T47	1		T43	67
valid_sources[0x5a]	24979	1			T3	1		T65	1		T5	2
valid_sources[0x5b]	23605	1			T5	1		T21	1		T117	1
valid_sources[0x5c]	23008	1			T23	2		T24	1		T5	2
valid_sources[0x5d]	23348	1			T3	1		T65	1		T15	2
valid_sources[0x5e]	23034	1			T15	1		T21	1		T117	2
valid_sources[0x5f]	24953	1			T5	2		T47	2		T13	5
valid_sources[0x60]	24420	1			T3	2		T24	2		T10	1
valid_sources[0x61]	26440	1			T3	1		T23	1		T24	1
valid_sources[0x62]	22893	1			T2	2		T23	2		T24	1
valid_sources[0x63]	23386	1			T2	1		T3	2		T5	2
valid_sources[0x64]	23860	1			T2	1		T22	1		T23	2
valid_sources[0x65]	27492	1			T24	1		T15	3		T5	2
valid_sources[0x66]	25197	1			T3	1		T5	3		T44	5
valid_sources[0x67]	24612	1			T2	1		T25	2		T5	1
valid_sources[0x68]	23953	1			T33	1		T44	7		T12	3
valid_sources[0x69]	24629	1			T3	1		T24	1		T26	4
valid_sources[0x6a]	24456	1			T5	3		T44	2		T114	3
valid_sources[0x6b]	22605	1			T65	1		T5	1		T20	3
valid_sources[0x6c]	23178	1			T25	1		T10	1		T5	2
valid_sources[0x6d]	26161	1			T3	3		T25	2		T5	2
valid_sources[0x6e]	24336	1			T24	3		T10	1		T5	1
valid_sources[0x6f]	23259	1			T24	1		T117	1		T40	150
valid_sources[0x70]	25319	1			T22	1		T15	1		T5	1
valid_sources[0x71]	23895	1			T24	1		T13	2		T40	150
valid_sources[0x72]	22562	1			T5	1		T52	4		T13	1
valid_sources[0x73]	27240	1			T5	4		T21	1		T117	2
valid_sources[0x74]	22930	1			T5	4		T21	1		T117	2
valid_sources[0x75]	24116	1			T2	8		T25	1		T15	2
valid_sources[0x76]	24335	1			T24	2		T21	3		T114	3
valid_sources[0x77]	24347	1			T24	1		T25	2		T5	1
valid_sources[0x78]	24411	1			T5	2		T94	2		T49	1
valid_sources[0x79]	25780	1			T24	1		T5	1		T48	1
valid_sources[0x7a]	23498	1			T24	1		T10	1		T15	1
valid_sources[0x7b]	26185	1			T45	102		T52	3		T13	1
valid_sources[0x7c]	25667	1			T3	1		T6	2		T12	3
valid_sources[0x7d]	24621	1			T24	3		T20	2		T251	96
valid_sources[0x7e]	22938	1			T5	1		T6	3		T21	1
valid_sources[0x7f]	25157	1			T5	1		T114	3		T84	5
valid_sources[0x80]	24807	1			T3	1		T10	2		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1387757

1

T1

10

T2

7

T3

5

values[0x0]

all_enables

biggest_size

2063403

1

T1

8

T2

8

T3

9

values[0x1]

all_enables

biggest_size

2059754

1

T1

4

T2

1

T3

20