Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2714	1			T3	1		T11	7		T5	4
non_zero_bins[1]	1914	1			T3	2		T24	3		T20	2
zero	9125	1			T1	5		T2	5		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	491	1			T3	1		T24	1		T45	1
uni	3589	1			T3	2		T24	2		T26	1
gen	4438	1			T1	3		T2	3		T3	2
res	877	1			T11	2		T15	1		T5	1
ins	4358	1			T1	2		T2	2		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9021

1

T1

2

T2

2

T3

7

mubi_true

4732

1

T1

3

T2

3

T23

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

14

1

T2

1

T65

1

T300

1

pass

13739

1

T1

5

T2

4

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	102	1			T40	1		T41	2		T56	1
upd	non_zero_bins[0]	pass	mubi_true	123	1			T93	1		T48	1		T41	4
upd	non_zero_bins[1]	pass	mubi_false	80	1			T3	1		T24	1		T45	1
upd	non_zero_bins[1]	pass	mubi_true	80	1			T117	1		T40	2		T237	1
upd	zero	pass	mubi_false	54	1			T84	1		T40	1		T41	1
upd	zero	pass	mubi_true	52	1			T40	1		T210	1		T113	1
uni	zero	pass	mubi_false	2674	1			T3	2		T24	2		T11	1
uni	zero	pass	mubi_true	915	1			T26	1		T5	1		T94	1
gen	non_zero_bins[0]	pass	mubi_false	488	1			T11	1		T5	2		T44	1
gen	non_zero_bins[0]	pass	mubi_true	593	1			T11	3		T20	3		T47	1
gen	non_zero_bins[1]	pass	mubi_false	412	1			T3	1		T24	1		T20	1
gen	non_zero_bins[1]	pass	mubi_true	342	1			T251	1		T84	1		T40	1
gen	zero	fail	mubi_false	13	1			T2	1		T65	1		T300	1
gen	zero	pass	mubi_false	1874	1			T1	1		T3	1		T24	1
gen	zero	pass	mubi_true	716	1			T1	2		T2	2		T23	2
res	non_zero_bins[0]	pass	mubi_false	188	1			T11	2		T21	1		T47	1
res	non_zero_bins[0]	pass	mubi_true	225	1			T20	2		T13	2		T40	3
res	non_zero_bins[1]	pass	mubi_false	156	1			T114	1		T41	2		T51	2
res	non_zero_bins[1]	pass	mubi_true	128	1			T21	3		T12	2		T40	1
res	zero	fail	mubi_false	1	1			T164	1		-	-		-	-
res	zero	pass	mubi_false	95	1			T15	1		T5	1		T43	1
res	zero	pass	mubi_true	84	1			T40	1		T41	1		T42	2
ins	non_zero_bins[0]	pass	mubi_false	497	1			T3	1		T11	1		T251	1
ins	non_zero_bins[0]	pass	mubi_true	498	1			T5	2		T251	1		T49	1
ins	non_zero_bins[1]	pass	mubi_false	345	1			T24	1		T45	1		T93	1
ins	non_zero_bins[1]	pass	mubi_true	371	1			T20	1		T21	2		T44	1
ins	zero	pass	mubi_false	2042	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	605	1			T1	1		T2	1		T23	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded