Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T23

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T35,T36
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T200,T208
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T21,T209,T179
DataWait->Error	99	Covered	T83,T7,T16
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T111,T210,T211
EndPointClear->Error	99	Covered	T35,T36,T212
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T2,T23
Idle->Error	99	Covered	T4,T83,T104

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T35,T36
default	-	-	-	-	Covered	T36,T104,T105

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T35,T36
0	1	Covered	T1,T2,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1539909406	1108436	0	0
FpvSecCmErrorStEscalate_A	1539909406	1116570	0	0
u_state_regs_A	1539874464	1538563490	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539909406	1108436	0	0
T4	14490	7756	0	0
T5	89565	0	0	0
T6	5551	0	0	0
T7	0	7784	0	0
T11	44184	0	0	0
T15	15267	0	0	0
T16	0	1624	0	0
T20	68159	0	0	0
T35	0	7490	0	0
T36	0	3212	0	0
T46	15351	0	0	0
T58	19572	0	0	0
T65	14364	0	0	0
T66	6237	0	0	0
T83	0	1330	0	0
T104	0	2470	0	0
T105	0	7860	0	0
T106	0	4354	0	0
T207	0	8001	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539909406	1116570	0	0
T4	14490	7763	0	0
T5	89565	0	0	0
T6	5551	0	0	0
T7	0	7791	0	0
T11	44184	0	0	0
T15	15267	0	0	0
T16	0	1631	0	0
T20	68159	0	0	0
T35	0	7497	0	0
T36	0	3219	0	0
T46	15351	0	0	0
T58	19572	0	0	0
T65	14364	0	0	0
T66	6237	0	0	0
T83	0	1337	0	0
T104	0	2477	0	0
T105	0	7867	0	0
T106	0	4361	0	0
T207	0	8008	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539874464	1538563490	0	0
T1	11886	11221	0	0
T2	12432	11809	0	0
T3	14161	13692	0	0
T4	14378	13608	0	0
T10	13874	13475	0	0
T22	7175	6566	0	0
T23	12096	11410	0	0
T24	41699	41314	0	0
T25	8512	8064	0	0
T26	10759	10332	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T35,T36
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T156,T213
DataWait->Error	99	Covered	T7,T64,T177
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T111,T210,T211
EndPointClear->Error	99	Covered	T35,T212,T62
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T2,T23
Idle->Error	99	Covered	T4,T83,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T35,T36
default	-	-	-	-	Covered	T36,T104,T105

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T35,T36
0	1	Covered	T1,T2,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	219987058	157148	0	0
FpvSecCmErrorStEscalate_A	219987058	158310	0	0
u_state_regs_A	219952116	219764834	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	157148	0	0
T4	2070	1108	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1112	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	232	0	0
T20	9737	0	0	0
T35	0	1070	0	0
T36	0	416	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	190	0	0
T104	0	310	0	0
T105	0	1080	0	0
T106	0	622	0	0
T207	0	1143	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	158310	0	0
T4	2070	1109	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1113	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	233	0	0
T20	9737	0	0	0
T35	0	1071	0	0
T36	0	417	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	191	0	0
T104	0	311	0	0
T105	0	1081	0	0
T106	0	623	0	0
T207	0	1144	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219952116	219764834	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	1958	1848	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T24,T11
DataWait	75	Covered	T23,T24,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T35,T36
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T24,T11
DataWait->AckPls	80	Covered	T23,T24,T11
DataWait->Disabled	107	Covered	T21,T180,T214
DataWait->Error	99	Covered	T83,T16,T59
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T111,T210,T211
EndPointClear->Error	99	Covered	T35,T36,T212
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T24,T11
Idle->Disabled	107	Covered	T1,T2,T23
Idle->Error	99	Covered	T4,T104,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T24,T11
Idle	-	1	0	-	Covered	T23,T24,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T24,T11
DataWait	-	-	-	0	Covered	T23,T24,T11
AckPls	-	-	-	-	Covered	T23,T24,T11
Error	-	-	-	-	Covered	T4,T35,T36
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T35,T36
0	1	Covered	T1,T2,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	219987058	158548	0	0
FpvSecCmErrorStEscalate_A	219987058	159710	0	0
u_state_regs_A	219987058	219799776	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	158548	0	0
T4	2070	1108	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1112	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	232	0	0
T20	9737	0	0	0
T35	0	1070	0	0
T36	0	466	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	190	0	0
T104	0	360	0	0
T105	0	1130	0	0
T106	0	622	0	0
T207	0	1143	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	159710	0	0
T4	2070	1109	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1113	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	233	0	0
T20	9737	0	0	0
T35	0	1071	0	0
T36	0	467	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	191	0	0
T104	0	361	0	0
T105	0	1131	0	0
T106	0	623	0	0
T207	0	1144	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T46,T45
DataWait	75	Covered	T24,T46,T45
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T35,T36
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T46,T45
DataWait->AckPls	80	Covered	T24,T46,T45
DataWait->Disabled	107	Covered	T215,T216
DataWait->Error	99	Covered	T106,T198,T217
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T111,T210,T211
EndPointClear->Error	99	Covered	T35,T36,T212
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T24,T46,T45
Idle->Disabled	107	Covered	T1,T2,T23
Idle->Error	99	Covered	T4,T83,T104

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T24,T46,T45
Idle	-	1	0	-	Covered	T24,T46,T45
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T24,T46,T45
DataWait	-	-	-	0	Covered	T24,T46,T45
AckPls	-	-	-	-	Covered	T24,T46,T45
Error	-	-	-	-	Covered	T4,T35,T36
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T35,T36
0	1	Covered	T1,T2,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	219987058	158548	0	0
FpvSecCmErrorStEscalate_A	219987058	159710	0	0
u_state_regs_A	219987058	219799776	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	158548	0	0
T4	2070	1108	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1112	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	232	0	0
T20	9737	0	0	0
T35	0	1070	0	0
T36	0	466	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	190	0	0
T104	0	360	0	0
T105	0	1130	0	0
T106	0	622	0	0
T207	0	1143	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	159710	0	0
T4	2070	1109	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1113	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	233	0	0
T20	9737	0	0	0
T35	0	1071	0	0
T36	0	467	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	191	0	0
T104	0	361	0	0
T105	0	1131	0	0
T106	0	623	0	0
T207	0	1144	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T47,T33,T48
DataWait	75	Covered	T47,T33,T48
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T35,T36
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T47,T33,T48
DataWait->AckPls	80	Covered	T47,T33,T48
DataWait->Disabled	107	Covered	T218,T219,T220
DataWait->Error	99	Covered	T221,T172,T222
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T111,T210,T211
EndPointClear->Error	99	Covered	T35,T36,T212
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T47,T33,T48
Idle->Disabled	107	Covered	T1,T2,T23
Idle->Error	99	Covered	T4,T83,T104

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T47,T33,T48
Idle	-	1	0	-	Covered	T47,T33,T48
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T47,T33,T48
DataWait	-	-	-	0	Covered	T47,T48,T44
AckPls	-	-	-	-	Covered	T47,T33,T48
Error	-	-	-	-	Covered	T4,T35,T36
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T35,T36
0	1	Covered	T1,T2,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	219987058	158548	0	0
FpvSecCmErrorStEscalate_A	219987058	159710	0	0
u_state_regs_A	219987058	219799776	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	158548	0	0
T4	2070	1108	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1112	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	232	0	0
T20	9737	0	0	0
T35	0	1070	0	0
T36	0	466	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	190	0	0
T104	0	360	0	0
T105	0	1130	0	0
T106	0	622	0	0
T207	0	1143	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	159710	0	0
T4	2070	1109	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1113	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	233	0	0
T20	9737	0	0	0
T35	0	1071	0	0
T36	0	467	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	191	0	0
T104	0	361	0	0
T105	0	1131	0	0
T106	0	623	0	0
T207	0	1144	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T47,T44
DataWait	75	Covered	T24,T47,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T35,T36
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T47,T44
DataWait->AckPls	80	Covered	T24,T47,T44
DataWait->Disabled	107	Covered	T223,T224
DataWait->Error	99	Covered	T197,T77,T206
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T111,T210,T211
EndPointClear->Error	99	Covered	T35,T36,T212
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T24,T47,T44
Idle->Disabled	107	Covered	T1,T2,T23
Idle->Error	99	Covered	T4,T83,T104

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T24,T47,T44
Idle	-	1	0	-	Covered	T24,T47,T44
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T24,T47,T44
DataWait	-	-	-	0	Covered	T24,T47,T44
AckPls	-	-	-	-	Covered	T24,T47,T44
Error	-	-	-	-	Covered	T4,T35,T36
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T35,T36
0	1	Covered	T1,T2,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	219987058	158548	0	0
FpvSecCmErrorStEscalate_A	219987058	159710	0	0
u_state_regs_A	219987058	219799776	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	158548	0	0
T4	2070	1108	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1112	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	232	0	0
T20	9737	0	0	0
T35	0	1070	0	0
T36	0	466	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	190	0	0
T104	0	360	0	0
T105	0	1130	0	0
T106	0	622	0	0
T207	0	1143	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	159710	0	0
T4	2070	1109	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1113	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	233	0	0
T20	9737	0	0	0
T35	0	1071	0	0
T36	0	467	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	191	0	0
T104	0	361	0	0
T105	0	1131	0	0
T106	0	623	0	0
T207	0	1144	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T43,T44
DataWait	75	Covered	T24,T43,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T35,T36
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T200
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T43,T44
DataWait->AckPls	80	Covered	T24,T43,T44
DataWait->Disabled	107	Covered	T209,T179,T225
DataWait->Error	99	Covered	T128,T165,T193
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T111,T210,T211
EndPointClear->Error	99	Covered	T35,T36,T212
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T24,T43,T44
Idle->Disabled	107	Covered	T1,T2,T23
Idle->Error	99	Covered	T4,T83,T104

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T24,T43,T44
Idle	-	1	0	-	Covered	T24,T43,T44
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T24,T43,T44
DataWait	-	-	-	0	Covered	T24,T43,T44
AckPls	-	-	-	-	Covered	T24,T43,T44
Error	-	-	-	-	Covered	T4,T35,T36
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T35,T36
0	1	Covered	T1,T2,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	219987058	158548	0	0
FpvSecCmErrorStEscalate_A	219987058	159710	0	0
u_state_regs_A	219987058	219799776	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	158548	0	0
T4	2070	1108	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1112	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	232	0	0
T20	9737	0	0	0
T35	0	1070	0	0
T36	0	466	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	190	0	0
T104	0	360	0	0
T105	0	1130	0	0
T106	0	622	0	0
T207	0	1143	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	159710	0	0
T4	2070	1109	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1113	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	233	0	0
T20	9737	0	0	0
T35	0	1071	0	0
T36	0	467	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	191	0	0
T104	0	361	0	0
T105	0	1131	0	0
T106	0	623	0	0
T207	0	1144	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T45,T21
DataWait	75	Covered	T10,T45,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T35,T36
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T208
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T45,T21
DataWait->AckPls	80	Covered	T10,T45,T21
DataWait->Disabled	107	Covered	T130,T131,T174
DataWait->Error	99	Covered	T9,T63,T71
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T111,T210,T211
EndPointClear->Error	99	Covered	T35,T36,T212
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T45,T21
Idle->Disabled	107	Covered	T1,T2,T23
Idle->Error	99	Covered	T4,T83,T104

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T45,T21
Idle	-	1	0	-	Covered	T10,T45,T21
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T45,T21
DataWait	-	-	-	0	Covered	T10,T45,T21
AckPls	-	-	-	-	Covered	T10,T45,T21
Error	-	-	-	-	Covered	T4,T35,T36
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T35,T36
0	1	Covered	T1,T2,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	219987058	158548	0	0
FpvSecCmErrorStEscalate_A	219987058	159710	0	0
u_state_regs_A	219987058	219799776	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	158548	0	0
T4	2070	1108	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1112	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	232	0	0
T20	9737	0	0	0
T35	0	1070	0	0
T36	0	466	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	190	0	0
T104	0	360	0	0
T105	0	1130	0	0
T106	0	622	0	0
T207	0	1143	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	159710	0	0
T4	2070	1109	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1113	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	233	0	0
T20	9737	0	0	0
T35	0	1071	0	0
T36	0	467	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	191	0	0
T104	0	361	0	0
T105	0	1131	0	0
T106	0	623	0	0
T207	0	1144	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0