Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T33,T37
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T32,T39
1	0	1	Covered	T1,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T58

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	439226546	661421	0	0
DepthKnown_A	439974116	439599552	0	0
RvalidKnown_A	439974116	439599552	0	0
WreadyKnown_A	439974116	439599552	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	439600448	742969	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439226546	661421	0	0
T1	3396	317	0	0
T2	3552	0	0	0
T3	4046	0	0	0
T4	712	0	0	0
T10	3964	444	0	0
T11	0	8555	0	0
T12	0	1251	0	0
T15	0	579	0	0
T20	0	13573	0	0
T21	0	6628	0	0
T22	2050	0	0	0
T23	3456	0	0	0
T24	11914	0	0	0
T25	2432	0	0	0
T26	3074	0	0	0
T43	0	478	0	0
T46	0	504	0	0
T58	0	656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439974116	439599552	0	0
T1	3396	3206	0	0
T2	3552	3374	0	0
T3	4046	3912	0	0
T4	4140	3920	0	0
T10	3964	3850	0	0
T22	2050	1876	0	0
T23	3456	3260	0	0
T24	11914	11804	0	0
T25	2432	2304	0	0
T26	3074	2952	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439974116	439599552	0	0
T1	3396	3206	0	0
T2	3552	3374	0	0
T3	4046	3912	0	0
T4	4140	3920	0	0
T10	3964	3850	0	0
T22	2050	1876	0	0
T23	3456	3260	0	0
T24	11914	11804	0	0
T25	2432	2304	0	0
T26	3074	2952	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439974116	439599552	0	0
T1	3396	3206	0	0
T2	3552	3374	0	0
T3	4046	3912	0	0
T4	4140	3920	0	0
T10	3964	3850	0	0
T22	2050	1876	0	0
T23	3456	3260	0	0
T24	11914	11804	0	0
T25	2432	2304	0	0
T26	3074	2952	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	439600448	742969	0	0
T1	3396	317	0	0
T2	3552	0	0	0
T3	4046	0	0	0
T4	4140	0	0	0
T6	0	16	0	0
T10	3964	444	0	0
T11	0	8555	0	0
T15	0	579	0	0
T20	0	13573	0	0
T21	0	6628	0	0
T22	2050	0	0	0
T23	3456	0	0	0
T24	11914	0	0	0
T25	2432	0	0	0
T26	3074	0	0	0
T35	0	111	0	0
T43	0	478	0	0
T46	0	504	0	0
T58	0	656	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T99,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T100
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T101,T102
1	0	1	Covered	T1,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T11,T15,T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	219613273	324884	0	0
DepthKnown_A	219987058	219799776	0	0
RvalidKnown_A	219987058	219799776	0	0
WreadyKnown_A	219987058	219799776	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	219800224	365553	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219613273	324884	0	0
T1	1698	160	0	0
T2	1776	0	0	0
T3	2023	0	0	0
T4	356	0	0	0
T10	1982	223	0	0
T11	0	4252	0	0
T12	0	623	0	0
T15	0	279	0	0
T20	0	6754	0	0
T21	0	3304	0	0
T22	1025	0	0	0
T23	1728	0	0	0
T24	5957	0	0	0
T25	1216	0	0	0
T26	1537	0	0	0
T43	0	240	0	0
T46	0	259	0	0
T58	0	336	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	219800224	365553	0	0
T1	1698	160	0	0
T2	1776	0	0	0
T3	2023	0	0	0
T4	2070	0	0	0
T10	1982	223	0	0
T11	0	4252	0	0
T15	0	279	0	0
T20	0	6754	0	0
T21	0	3304	0	0
T22	1025	0	0	0
T23	1728	0	0	0
T24	5957	0	0	0
T25	1216	0	0	0
T26	1537	0	0	0
T35	0	111	0	0
T43	0	240	0	0
T46	0	259	0	0
T58	0	336	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T33,T37
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T39,T103
1	0	1	Covered	T1,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	219613273	336537	0	0
DepthKnown_A	219987058	219799776	0	0
RvalidKnown_A	219987058	219799776	0	0
WreadyKnown_A	219987058	219799776	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	219800224	377416	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219613273	336537	0	0
T1	1698	157	0	0
T2	1776	0	0	0
T3	2023	0	0	0
T4	356	0	0	0
T10	1982	221	0	0
T11	0	4303	0	0
T12	0	628	0	0
T15	0	300	0	0
T20	0	6819	0	0
T21	0	3324	0	0
T22	1025	0	0	0
T23	1728	0	0	0
T24	5957	0	0	0
T25	1216	0	0	0
T26	1537	0	0	0
T43	0	238	0	0
T46	0	245	0	0
T58	0	320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	219800224	377416	0	0
T1	1698	157	0	0
T2	1776	0	0	0
T3	2023	0	0	0
T4	2070	0	0	0
T6	0	16	0	0
T10	1982	221	0	0
T11	0	4303	0	0
T15	0	300	0	0
T20	0	6819	0	0
T21	0	3324	0	0
T22	1025	0	0	0
T23	1728	0	0	0
T24	5957	0	0	0
T25	1216	0	0	0
T26	1537	0	0	0
T43	0	238	0	0
T46	0	245	0	0
T58	0	320	0	0