Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	150	1			T2	1		T20	1		T22	1
auto_req_mode	145	1			T9	1		T10	1		T11	1
sw_mode	3033	1			T3	45		T5	3		T48	2

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

284

1

T2

1

T20

1

T22

1

single

116

1

T9

1

T12

1

T67

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1924	1			T2	1		T3	45		T20	1
auto[2]	120	1			T13	1		T311	9		T312	1
auto[3]	72	1			T12	1		T40	1		T287	1
auto[4]	135	1			T313	1		T314	1		T315	1
auto[5]	177	1			T81	1		T14	1		T243	5
auto[6]	42	1			T5	3		T84	1		T98	1
auto[7]	858	1			T9	1		T10	1		T48	2

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	85	1			T2	1		T20	1		T22	1
auto[1]	auto_req_mode	82	1			T11	1		T67	1		T316	1
auto[1]	sw_mode	1757	1			T3	45		T34	32		T23	1
auto[2]	boot_req_mode	4	1			T317	1		T318	1		T319	1
auto[2]	auto_req_mode	4	1			T13	1		T312	1		T320	1
auto[2]	sw_mode	112	1			T311	9		T321	57		T322	8
auto[3]	boot_req_mode	4	1			T40	1		T287	1		T323	1
auto[3]	auto_req_mode	4	1			T12	1		T324	1		T325	1
auto[3]	sw_mode	64	1			T326	1		T327	1		T328	1
auto[4]	boot_req_mode	4	1			T313	1		T315	1		T329	1
auto[4]	auto_req_mode	3	1			T330	1		T242	1		T331	1
auto[4]	sw_mode	128	1			T314	1		T332	1		T333	9
auto[5]	boot_req_mode	5	1			T334	1		T335	1		T336	1
auto[5]	auto_req_mode	1	1			T14	1		-	-		-	-
auto[5]	sw_mode	171	1			T81	1		T243	5		T337	1
auto[6]	boot_req_mode	6	1			T84	1		T338	1		T339	1
auto[6]	auto_req_mode	8	1			T340	1		T341	1		T342	1
auto[6]	sw_mode	28	1			T5	3		T98	1		T343	4
auto[7]	boot_req_mode	42	1			T37	1		T46	1		T64	1
auto[7]	auto_req_mode	43	1			T9	1		T10	1		T19	1
auto[7]	sw_mode	773	1			T48	2		T73	13		T35	48