Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	698870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5576839

1

T1

17

T2

5

T3

99780

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1662708	1			T1	34		T2	1		T3	29213
values[0x0]	2132858	1			T1	12		T2	2		T3	37912
values[0x1]	2480143	1			T1	10		T2	3		T3	44489

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	347838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5927871

1

T1

23

T2

5

T3

105960

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24126	1			T3	406		T20	1		T73	3
valid_sources[0x01]	27073	1			T3	430		T20	3		T11	1
valid_sources[0x02]	25638	1			T3	391		T9	5		T73	4
valid_sources[0x03]	25223	1			T3	420		T20	1		T9	21
valid_sources[0x04]	23809	1			T3	425		T73	10		T74	3
valid_sources[0x05]	24353	1			T1	2		T3	468		T20	1
valid_sources[0x06]	25196	1			T3	433		T20	1		T11	1
valid_sources[0x07]	24733	1			T3	486		T73	1		T12	2
valid_sources[0x08]	23981	1			T1	1		T3	461		T20	1
valid_sources[0x09]	24573	1			T3	429		T20	1		T15	2
valid_sources[0x0a]	24076	1			T3	452		T73	1		T39	2
valid_sources[0x0b]	24559	1			T1	1		T3	459		T20	2
valid_sources[0x0c]	24165	1			T3	422		T20	1		T21	1
valid_sources[0x0d]	24155	1			T3	434		T15	2		T11	1
valid_sources[0x0e]	24186	1			T3	460		T22	1		T73	3
valid_sources[0x0f]	23423	1			T3	443		T20	1		T9	2
valid_sources[0x10]	24553	1			T3	439		T15	2		T73	4
valid_sources[0x11]	22740	1			T3	441		T15	1		T73	2
valid_sources[0x12]	24214	1			T3	449		T73	4		T12	2
valid_sources[0x13]	25693	1			T1	1		T3	432		T9	4
valid_sources[0x14]	24923	1			T3	466		T20	1		T48	7
valid_sources[0x15]	24450	1			T3	435		T11	1		T73	5
valid_sources[0x16]	25441	1			T3	425		T9	5		T73	4
valid_sources[0x17]	25917	1			T1	1		T3	455		T21	1
valid_sources[0x18]	24491	1			T1	1		T3	413		T11	1
valid_sources[0x19]	22714	1			T3	414		T20	1		T73	5
valid_sources[0x1a]	24897	1			T3	397		T15	1		T11	2
valid_sources[0x1b]	23370	1			T1	3		T3	458		T20	1
valid_sources[0x1c]	25102	1			T3	435		T20	1		T73	3
valid_sources[0x1d]	25881	1			T1	1		T3	432		T73	8
valid_sources[0x1e]	24675	1			T3	445		T15	2		T11	1
valid_sources[0x1f]	23341	1			T1	2		T3	381		T20	1
valid_sources[0x20]	25686	1			T1	4		T3	435		T11	1
valid_sources[0x21]	24733	1			T3	426		T20	2		T11	1
valid_sources[0x22]	24048	1			T2	6		T3	431		T9	8
valid_sources[0x23]	24893	1			T3	439		T73	4		T74	1
valid_sources[0x24]	25272	1			T3	412		T73	5		T45	1
valid_sources[0x25]	28226	1			T3	418		T11	2		T73	4
valid_sources[0x26]	23907	1			T3	456		T20	3		T73	4
valid_sources[0x27]	26063	1			T3	430		T15	3		T11	1
valid_sources[0x28]	23263	1			T3	490		T73	10		T75	1
valid_sources[0x29]	25035	1			T3	442		T73	4		T12	1
valid_sources[0x2a]	26400	1			T3	465		T20	1		T73	7
valid_sources[0x2b]	24689	1			T3	438		T9	5		T11	1
valid_sources[0x2c]	24940	1			T3	430		T20	1		T11	2
valid_sources[0x2d]	23976	1			T3	437		T73	3		T12	1
valid_sources[0x2e]	23796	1			T3	442		T30	16		T73	1
valid_sources[0x2f]	23700	1			T3	426		T48	14		T73	2
valid_sources[0x30]	25752	1			T3	389		T73	10		T12	1
valid_sources[0x31]	26430	1			T3	435		T20	3		T11	1
valid_sources[0x32]	24315	1			T3	403		T20	2		T11	1
valid_sources[0x33]	24945	1			T3	402		T20	1		T73	8
valid_sources[0x34]	23898	1			T3	410		T20	1		T21	1
valid_sources[0x35]	23294	1			T1	1		T3	452		T20	2
valid_sources[0x36]	24559	1			T3	440		T20	3		T21	1
valid_sources[0x37]	23771	1			T1	1		T3	458		T73	2
valid_sources[0x38]	25093	1			T1	1		T3	426		T20	2
valid_sources[0x39]	23878	1			T3	438		T20	2		T11	1
valid_sources[0x3a]	24324	1			T3	428		T20	1		T9	15
valid_sources[0x3b]	23128	1			T3	411		T20	1		T9	5
valid_sources[0x3c]	24962	1			T3	386		T73	9		T45	1
valid_sources[0x3d]	24220	1			T3	412		T73	2		T39	1
valid_sources[0x3e]	25138	1			T3	468		T20	1		T9	20
valid_sources[0x3f]	24349	1			T3	437		T73	5		T34	208
valid_sources[0x40]	24137	1			T3	461		T73	2		T34	197
valid_sources[0x41]	24486	1			T3	450		T73	8		T34	232
valid_sources[0x42]	23925	1			T3	476		T73	2		T12	2
valid_sources[0x43]	23554	1			T3	427		T20	3		T15	38
valid_sources[0x44]	24669	1			T1	3		T3	430		T48	3
valid_sources[0x45]	24304	1			T3	428		T9	19		T11	2
valid_sources[0x46]	25179	1			T3	445		T21	2		T73	4
valid_sources[0x47]	25929	1			T3	417		T20	1		T73	2
valid_sources[0x48]	24487	1			T3	459		T11	2		T73	8
valid_sources[0x49]	25073	1			T3	456		T73	6		T12	1
valid_sources[0x4a]	25575	1			T3	445		T20	1		T73	6
valid_sources[0x4b]	24002	1			T3	456		T20	3		T11	1
valid_sources[0x4c]	24656	1			T3	433		T11	1		T48	9
valid_sources[0x4d]	24463	1			T3	431		T20	3		T73	6
valid_sources[0x4e]	24453	1			T3	435		T20	1		T21	1
valid_sources[0x4f]	25420	1			T1	1		T3	427		T20	1
valid_sources[0x50]	23770	1			T3	457		T21	1		T22	1
valid_sources[0x51]	24189	1			T3	434		T21	1		T73	5
valid_sources[0x52]	24615	1			T3	417		T20	1		T9	3
valid_sources[0x53]	24109	1			T1	1		T3	417		T73	6
valid_sources[0x54]	25639	1			T1	1		T3	414		T73	2
valid_sources[0x55]	26608	1			T3	466		T20	1		T9	1
valid_sources[0x56]	22528	1			T3	444		T20	5		T11	3
valid_sources[0x57]	24049	1			T3	471		T9	3		T73	1
valid_sources[0x58]	25452	1			T3	436		T21	2		T73	3
valid_sources[0x59]	23318	1			T3	444		T20	2		T73	2
valid_sources[0x5a]	24797	1			T3	437		T11	2		T73	2
valid_sources[0x5b]	24775	1			T3	460		T20	2		T9	26
valid_sources[0x5c]	23906	1			T3	438		T9	24		T11	1
valid_sources[0x5d]	22930	1			T3	441		T21	1		T11	1
valid_sources[0x5e]	24607	1			T3	432		T73	4		T34	150
valid_sources[0x5f]	24016	1			T3	417		T15	1		T11	1
valid_sources[0x60]	24014	1			T3	445		T20	1		T73	2
valid_sources[0x61]	23651	1			T3	488		T11	1		T73	7
valid_sources[0x62]	23990	1			T3	410		T20	1		T11	1
valid_sources[0x63]	24076	1			T3	462		T5	247		T73	6
valid_sources[0x64]	24679	1			T3	444		T9	16		T73	3
valid_sources[0x65]	28388	1			T3	453		T20	2		T73	6
valid_sources[0x66]	23581	1			T3	417		T20	1		T73	2
valid_sources[0x67]	23670	1			T3	426		T9	30		T73	3
valid_sources[0x68]	23877	1			T1	1		T3	456		T9	9
valid_sources[0x69]	23588	1			T3	462		T47	7		T73	4
valid_sources[0x6a]	24531	1			T3	449		T21	1		T73	6
valid_sources[0x6b]	23177	1			T1	1		T3	462		T21	1
valid_sources[0x6c]	25365	1			T3	444		T73	6		T12	1
valid_sources[0x6d]	24670	1			T3	400		T73	5		T34	166
valid_sources[0x6e]	24798	1			T3	430		T9	10		T73	7
valid_sources[0x6f]	24735	1			T3	416		T11	1		T73	5
valid_sources[0x70]	25488	1			T3	426		T20	2		T21	3
valid_sources[0x71]	25517	1			T3	434		T20	1		T47	3
valid_sources[0x72]	26001	1			T3	424		T73	3		T74	2
valid_sources[0x73]	25941	1			T3	425		T48	3		T73	1
valid_sources[0x74]	24339	1			T3	416		T20	1		T73	5
valid_sources[0x75]	25389	1			T3	445		T20	1		T9	2
valid_sources[0x76]	23981	1			T3	410		T73	4		T12	3
valid_sources[0x77]	25023	1			T3	477		T11	1		T73	3
valid_sources[0x78]	24477	1			T3	450		T20	2		T11	1
valid_sources[0x79]	25735	1			T3	463		T20	1		T21	1
valid_sources[0x7a]	24072	1			T3	458		T11	1		T73	4
valid_sources[0x7b]	24105	1			T3	432		T73	4		T34	206
valid_sources[0x7c]	23358	1			T1	2		T3	451		T20	1
valid_sources[0x7d]	24785	1			T1	1		T3	449		T21	1
valid_sources[0x7e]	24190	1			T3	453		T20	1		T9	6
valid_sources[0x7f]	23371	1			T3	414		T73	1		T34	194
valid_sources[0x80]	23295	1			T3	413		T20	1		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1404608

1

T1

8

T2

1

T3

25075

values[0x0]

all_enables

biggest_size

2087537

1

T1

5

T2

1

T3

37252

values[0x1]

all_enables

biggest_size

2084694

1

T1

4

T2

3

T3

37453