Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2814	1			T3	40		T9	2		T10	1
non_zero_bins[1]	1960	1			T3	18		T20	2		T9	5
zero	9735	1			T1	5		T2	4		T3	113

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	549	1			T3	11		T5	1		T73	1
uni	3887	1			T3	55		T20	2		T9	1
gen	4590	1			T1	3		T2	2		T3	45
res	886	1			T3	5		T20	1		T9	2
ins	4597	1			T1	2		T2	2		T3	55

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9631

1

T1

2

T3

123

T20

6

mubi_true

4878

1

T1

3

T2

4

T3

48

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

23

1

T15

1

T45

1

T285

1

pass

14486

1

T1

5

T2

4

T3

171

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	139	1			T3	3		T73	1		T34	3
upd	non_zero_bins[0]	pass	mubi_true	136	1			T3	1		T5	1		T34	1
upd	non_zero_bins[1]	pass	mubi_false	80	1			T3	1		T35	1		T70	2
upd	non_zero_bins[1]	pass	mubi_true	91	1			T3	3		T35	2		T96	3
upd	zero	pass	mubi_false	45	1			T3	1		T35	1		T70	1
upd	zero	pass	mubi_true	58	1			T3	2		T40	1		T223	1
uni	zero	pass	mubi_false	2838	1			T3	44		T20	2		T9	1
uni	zero	pass	mubi_true	1049	1			T3	11		T5	1		T48	1
gen	non_zero_bins[0]	pass	mubi_false	529	1			T3	7		T10	1		T73	2
gen	non_zero_bins[0]	pass	mubi_true	490	1			T3	7		T12	7		T67	3
gen	non_zero_bins[1]	pass	mubi_false	402	1			T3	3		T10	3		T48	1
gen	non_zero_bins[1]	pass	mubi_true	345	1			T3	4		T20	1		T9	4
gen	zero	fail	mubi_false	21	1			T15	1		T45	1		T285	1
gen	zero	pass	mubi_false	2027	1			T1	1		T3	21		T20	1
gen	zero	pass	mubi_true	776	1			T1	2		T2	2		T3	3
res	non_zero_bins[0]	pass	mubi_false	212	1			T3	2		T9	2		T48	1
res	non_zero_bins[0]	pass	mubi_true	195	1			T3	2		T34	1		T35	3
res	non_zero_bins[1]	pass	mubi_false	145	1			T10	2		T73	1		T34	1
res	non_zero_bins[1]	pass	mubi_true	139	1			T73	1		T12	2		T35	2
res	zero	fail	mubi_false	2	1			T160	1		T286	1		-	-
res	zero	pass	mubi_false	102	1			T3	1		T20	1		T34	1
res	zero	pass	mubi_true	91	1			T11	2		T67	4		T70	1
ins	non_zero_bins[0]	pass	mubi_false	579	1			T3	9		T55	1		T11	1
ins	non_zero_bins[0]	pass	mubi_true	534	1			T3	9		T73	2		T67	1
ins	non_zero_bins[1]	pass	mubi_false	385	1			T3	2		T20	1		T5	1
ins	non_zero_bins[1]	pass	mubi_true	373	1			T3	5		T9	1		T10	1
ins	zero	pass	mubi_false	2125	1			T1	1		T3	29		T20	1
ins	zero	pass	mubi_true	601	1			T1	1		T2	2		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded