Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T27,T31
1	1	0	Not Covered
1	1	1	Covered	T4,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T26,T29,T33
1	0	1	Covered	T4,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435095756	601953	0	0
DepthKnown_A	435798228	435422100	0	0
RvalidKnown_A	435798228	435422100	0	0
WreadyKnown_A	435798228	435422100	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435421120	676189	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435095756	601953	0	0
T5	9824	0	0	0
T6	0	63	0	0
T9	12384	7329	0	0
T10	12484	7971	0	0
T11	4048	2242	0	0
T12	0	837	0	0
T15	4010	353	0	0
T22	2014	0	0	0
T30	198	0	0	0
T39	0	463	0	0
T47	2472	0	0	0
T48	9820	0	0	0
T55	3016	0	0	0
T67	0	2139	0	0
T74	0	57	0	0
T75	0	621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435798228	435422100	0	0
T1	4146	3990	0	0
T2	2400	2290	0	0
T3	625596	625580	0	0
T4	6084	5782	0	0
T9	12384	12280	0	0
T10	12484	12348	0	0
T15	4010	3844	0	0
T20	7480	7360	0	0
T21	4982	4782	0	0
T22	2014	1860	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435798228	435422100	0	0
T1	4146	3990	0	0
T2	2400	2290	0	0
T3	625596	625580	0	0
T4	6084	5782	0	0
T9	12384	12280	0	0
T10	12484	12348	0	0
T15	4010	3844	0	0
T20	7480	7360	0	0
T21	4982	4782	0	0
T22	2014	1860	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435798228	435422100	0	0
T1	4146	3990	0	0
T2	2400	2290	0	0
T3	625596	625580	0	0
T4	6084	5782	0	0
T9	12384	12280	0	0
T10	12484	12348	0	0
T15	4010	3844	0	0
T20	7480	7360	0	0
T21	4982	4782	0	0
T22	2014	1860	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435421120	676189	0	0
T4	6084	2294	0	0
T5	9824	0	0	0
T9	12384	7329	0	0
T10	12484	7971	0	0
T11	4048	2242	0	0
T12	0	837	0	0
T15	4010	353	0	0
T22	2014	0	0	0
T30	1232	278	0	0
T39	0	463	0	0
T47	2472	0	0	0
T55	3016	0	0	0
T67	0	2139	0	0
T74	0	57	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T59,T91,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T27
1	1	0	Not Covered
1	1	1	Covered	T4,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T26,T33,T92
1	0	1	Covered	T4,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	217547878	295646	0	0
DepthKnown_A	217899114	217711050	0	0
RvalidKnown_A	217899114	217711050	0	0
WreadyKnown_A	217899114	217711050	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217710560	332731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217547878	295646	0	0
T5	4912	0	0	0
T6	0	19	0	0
T9	6192	3657	0	0
T10	6242	3983	0	0
T11	2024	1106	0	0
T12	0	417	0	0
T15	2005	156	0	0
T22	1007	0	0	0
T30	99	0	0	0
T39	0	230	0	0
T47	1236	0	0	0
T48	4910	0	0	0
T55	1508	0	0	0
T67	0	1044	0	0
T74	0	23	0	0
T75	0	273	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217710560	332731	0	0
T4	3042	1151	0	0
T5	4912	0	0	0
T9	6192	3657	0	0
T10	6242	3983	0	0
T11	2024	1106	0	0
T12	0	417	0	0
T15	2005	156	0	0
T22	1007	0	0	0
T30	616	140	0	0
T39	0	230	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T67	0	1044	0	0
T74	0	23	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31
1	1	0	Not Covered
1	1	1	Covered	T4,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T93,T94
1	0	1	Covered	T4,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	217547878	306307	0	0
DepthKnown_A	217899114	217711050	0	0
RvalidKnown_A	217899114	217711050	0	0
WreadyKnown_A	217899114	217711050	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217710560	343458	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217547878	306307	0	0
T5	4912	0	0	0
T6	0	44	0	0
T9	6192	3672	0	0
T10	6242	3988	0	0
T11	2024	1136	0	0
T12	0	420	0	0
T15	2005	197	0	0
T22	1007	0	0	0
T30	99	0	0	0
T39	0	233	0	0
T47	1236	0	0	0
T48	4910	0	0	0
T55	1508	0	0	0
T67	0	1095	0	0
T74	0	34	0	0
T75	0	348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217710560	343458	0	0
T4	3042	1143	0	0
T5	4912	0	0	0
T9	6192	3672	0	0
T10	6242	3988	0	0
T11	2024	1136	0	0
T12	0	420	0	0
T15	2005	197	0	0
T22	1007	0	0	0
T30	616	138	0	0
T39	0	233	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T67	0	1095	0	0
T74	0	34	0	0