Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	663749	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5372047

1

T1

1

T2

3

T3

52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1596489	1			T1	1		T2	1		T3	44
values[0x0]	2050703	1			T1	4		T2	15		T3	31
values[0x1]	2388604	1			T1	4		T2	6		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	328315	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5707481

1

T1

2

T2

4

T3

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23585	1			T3	1		T8	1		T11	1
valid_sources[0x01]	24475	1			T3	3		T7	1		T8	1
valid_sources[0x02]	24271	1			T8	2		T6	8		T51	1
valid_sources[0x03]	23640	1			T3	6		T26	3		T49	2
valid_sources[0x04]	22599	1			T6	2		T23	2		T51	1
valid_sources[0x05]	23459	1			T11	1		T6	1		T23	1
valid_sources[0x06]	23115	1			T3	1		T49	1		T47	2
valid_sources[0x07]	20830	1			T3	1		T8	2		T26	1
valid_sources[0x08]	23149	1			T3	1		T7	1		T11	2
valid_sources[0x09]	24621	1			T3	1		T6	8		T54	1
valid_sources[0x0a]	24037	1			T7	1		T6	8		T54	1
valid_sources[0x0b]	22275	1			T6	5		T45	1		T40	227
valid_sources[0x0c]	25622	1			T46	264		T40	101		T41	409
valid_sources[0x0d]	24483	1			T3	2		T11	1		T6	1
valid_sources[0x0e]	25106	1			T26	1		T47	1		T6	2
valid_sources[0x0f]	23376	1			T3	3		T11	2		T26	1
valid_sources[0x10]	25088	1			T25	3		T26	3		T6	14
valid_sources[0x11]	26435	1			T25	1		T48	1		T6	4
valid_sources[0x12]	21114	1			T8	1		T11	2		T24	6
valid_sources[0x13]	22506	1			T11	1		T6	5		T23	1
valid_sources[0x14]	22983	1			T8	1		T26	1		T47	2
valid_sources[0x15]	24465	1			T3	1		T26	2		T6	2
valid_sources[0x16]	23182	1			T7	2		T49	1		T51	1
valid_sources[0x17]	24838	1			T3	5		T11	2		T6	5
valid_sources[0x18]	21142	1			T3	3		T25	2		T26	1
valid_sources[0x19]	23911	1			T3	1		T26	2		T6	1
valid_sources[0x1a]	23619	1			T3	1		T49	2		T40	261
valid_sources[0x1b]	22345	1			T25	1		T26	1		T6	5
valid_sources[0x1c]	22084	1			T11	5		T6	9		T51	1
valid_sources[0x1d]	22295	1			T26	1		T49	2		T6	3
valid_sources[0x1e]	24173	1			T3	1		T11	3		T25	1
valid_sources[0x1f]	22574	1			T48	9		T6	9		T44	2
valid_sources[0x20]	23592	1			T11	3		T48	3		T23	1
valid_sources[0x21]	24003	1			T24	10		T49	1		T47	1
valid_sources[0x22]	23501	1			T11	1		T26	2		T6	6
valid_sources[0x23]	22278	1			T11	2		T25	1		T26	1
valid_sources[0x24]	22425	1			T8	1		T24	2		T26	1
valid_sources[0x25]	24731	1			T3	1		T8	1		T11	1
valid_sources[0x26]	25332	1			T8	1		T26	1		T6	1
valid_sources[0x27]	23582	1			T3	1		T7	1		T6	3
valid_sources[0x28]	23572	1			T3	1		T11	1		T25	4
valid_sources[0x29]	21122	1			T7	2		T26	3		T6	1
valid_sources[0x2a]	24026	1			T3	1		T6	2		T23	2
valid_sources[0x2b]	24551	1			T26	2		T49	1		T6	6
valid_sources[0x2c]	22692	1			T26	1		T6	7		T54	3
valid_sources[0x2d]	23494	1			T24	1		T49	2		T54	6
valid_sources[0x2e]	24995	1			T25	1		T26	2		T6	3
valid_sources[0x2f]	24770	1			T3	1		T6	3		T23	2
valid_sources[0x30]	21813	1			T26	1		T49	1		T48	1
valid_sources[0x31]	24962	1			T25	1		T26	1		T49	2
valid_sources[0x32]	22791	1			T7	1		T26	2		T6	3
valid_sources[0x33]	23765	1			T49	1		T6	1		T44	1
valid_sources[0x34]	24556	1			T11	1		T26	1		T6	6
valid_sources[0x35]	21468	1			T25	2		T26	1		T6	6
valid_sources[0x36]	24571	1			T26	2		T6	3		T40	227
valid_sources[0x37]	21877	1			T3	1		T7	1		T26	4
valid_sources[0x38]	23250	1			T8	1		T26	2		T49	1
valid_sources[0x39]	22693	1			T26	1		T48	1		T47	4
valid_sources[0x3a]	23104	1			T48	1		T47	3		T62	1
valid_sources[0x3b]	23804	1			T3	3		T26	2		T62	1
valid_sources[0x3c]	23772	1			T3	2		T11	2		T6	6
valid_sources[0x3d]	23283	1			T8	1		T26	2		T48	1
valid_sources[0x3e]	24248	1			T7	1		T26	1		T6	17
valid_sources[0x3f]	21956	1			T8	1		T48	1		T6	1
valid_sources[0x40]	23219	1			T48	1		T6	1		T45	1
valid_sources[0x41]	25046	1			T7	2		T8	1		T49	1
valid_sources[0x42]	22103	1			T1	5		T8	1		T47	4
valid_sources[0x43]	22532	1			T3	1		T11	1		T26	1
valid_sources[0x44]	24448	1			T26	2		T49	1		T6	2
valid_sources[0x45]	22730	1			T26	1		T48	1		T6	5
valid_sources[0x46]	24772	1			T3	2		T26	2		T48	2
valid_sources[0x47]	24336	1			T7	2		T26	1		T47	1
valid_sources[0x48]	21078	1			T11	1		T26	3		T6	17
valid_sources[0x49]	24571	1			T24	3		T48	3		T44	2
valid_sources[0x4a]	24377	1			T7	1		T6	1		T62	1
valid_sources[0x4b]	23732	1			T26	3		T48	1		T6	2
valid_sources[0x4c]	24104	1			T24	1		T6	8		T23	1
valid_sources[0x4d]	24593	1			T26	1		T6	4		T54	1
valid_sources[0x4e]	23304	1			T24	3		T26	2		T6	3
valid_sources[0x4f]	26790	1			T3	1		T11	1		T6	2
valid_sources[0x50]	22738	1			T11	2		T26	3		T48	1
valid_sources[0x51]	23836	1			T26	1		T49	1		T6	1
valid_sources[0x52]	23394	1			T11	1		T26	3		T6	5
valid_sources[0x53]	25546	1			T8	1		T24	4		T26	1
valid_sources[0x54]	23063	1			T26	1		T6	4		T54	5
valid_sources[0x55]	23611	1			T8	1		T11	1		T26	2
valid_sources[0x56]	21971	1			T54	5		T40	23		T41	320
valid_sources[0x57]	25357	1			T3	3		T26	6		T6	2
valid_sources[0x58]	24335	1			T6	7		T44	8		T82	7
valid_sources[0x59]	23213	1			T26	4		T62	1		T44	2
valid_sources[0x5a]	26526	1			T26	2		T48	1		T6	1
valid_sources[0x5b]	23319	1			T3	1		T8	1		T24	1
valid_sources[0x5c]	22321	1			T8	1		T6	3		T40	10
valid_sources[0x5d]	24060	1			T7	4		T26	1		T6	1
valid_sources[0x5e]	24069	1			T11	2		T26	1		T6	1
valid_sources[0x5f]	23764	1			T26	1		T6	6		T54	1
valid_sources[0x60]	23632	1			T7	1		T49	1		T6	21
valid_sources[0x61]	22012	1			T8	1		T11	1		T26	1
valid_sources[0x62]	24463	1			T7	1		T26	2		T6	4
valid_sources[0x63]	24038	1			T26	1		T15	8		T49	1
valid_sources[0x64]	22889	1			T7	3		T26	2		T48	1
valid_sources[0x65]	24238	1			T3	2		T6	2		T51	1
valid_sources[0x66]	23379	1			T7	1		T11	1		T26	2
valid_sources[0x67]	23389	1			T26	1		T47	1		T6	1
valid_sources[0x68]	22888	1			T15	11		T48	1		T47	1
valid_sources[0x69]	24301	1			T7	5		T6	12		T23	2
valid_sources[0x6a]	21000	1			T3	2		T25	1		T6	3
valid_sources[0x6b]	22271	1			T24	2		T6	3		T54	1
valid_sources[0x6c]	23295	1			T11	2		T26	1		T48	1
valid_sources[0x6d]	19990	1			T11	1		T26	1		T23	1
valid_sources[0x6e]	23057	1			T3	1		T26	1		T49	1
valid_sources[0x6f]	23107	1			T7	4		T6	3		T23	1
valid_sources[0x70]	25420	1			T11	3		T49	2		T54	1
valid_sources[0x71]	22596	1			T3	1		T8	1		T24	17
valid_sources[0x72]	21526	1			T26	2		T6	2		T44	4
valid_sources[0x73]	22402	1			T26	1		T47	1		T6	1
valid_sources[0x74]	22927	1			T26	2		T6	8		T62	1
valid_sources[0x75]	24057	1			T47	1		T6	7		T44	2
valid_sources[0x76]	23158	1			T24	1		T47	1		T44	4
valid_sources[0x77]	23167	1			T7	1		T11	1		T25	1
valid_sources[0x78]	23172	1			T7	1		T26	2		T6	5
valid_sources[0x79]	21940	1			T3	1		T11	1		T26	2
valid_sources[0x7a]	21186	1			T25	3		T26	1		T6	2
valid_sources[0x7b]	22619	1			T24	9		T6	4		T23	1
valid_sources[0x7c]	24233	1			T3	2		T8	1		T24	2
valid_sources[0x7d]	20969	1			T11	1		T26	1		T45	4
valid_sources[0x7e]	23385	1			T8	1		T49	1		T6	10
valid_sources[0x7f]	23445	1			T3	1		T7	1		T26	1
valid_sources[0x80]	25184	1			T6	1		T54	2		T40	198

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1352236

1

T2

1

T3

5

T7

10

values[0x0]

all_enables

biggest_size

2008633

1

T2

2

T3

26

T7

32

values[0x1]

all_enables

biggest_size

2011178

1

T1

1

T3

21

T7

16