Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2596	1			T3	4		T11	5		T24	1
non_zero_bins[1]	1801	1			T3	3		T11	4		T24	2
zero	8943	1			T3	1		T7	4		T8	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	477	1			T24	1		T6	5		T46	1
uni	3513	1			T3	1		T24	2		T25	1
gen	4270	1			T3	4		T7	2		T8	2
res	813	1			T3	2		T11	4		T25	1
ins	4267	1			T3	1		T7	2		T8	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8788

1

T3

2

T7

1

T11

6

mubi_true

4552

1

T3

6

T7

3

T8

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

20

1

T120

1

T275

1

T281

1

pass

13320

1

T3

8

T7

4

T8

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	124	1			T6	2		T282	1		T41	1
upd	non_zero_bins[0]	pass	mubi_true	107	1			T6	1		T40	1		T41	1
upd	non_zero_bins[1]	pass	mubi_false	65	1			T6	1		T46	1		T54	1
upd	non_zero_bins[1]	pass	mubi_true	95	1			T24	1		T6	1		T40	1
upd	zero	pass	mubi_false	48	1			T41	1		T76	2		T105	3
upd	zero	pass	mubi_true	38	1			T76	1		T236	1		T237	1
uni	zero	pass	mubi_false	2615	1			T3	1		T24	2		T25	1
uni	zero	pass	mubi_true	898	1			T26	1		T49	1		T6	4
gen	non_zero_bins[0]	pass	mubi_false	491	1			T3	1		T11	4		T25	1
gen	non_zero_bins[0]	pass	mubi_true	479	1			T6	3		T44	1		T21	4
gen	non_zero_bins[1]	pass	mubi_false	377	1			T24	1		T6	2		T40	1
gen	non_zero_bins[1]	pass	mubi_true	318	1			T3	3		T6	1		T23	3
gen	zero	fail	mubi_false	19	1			T120	1		T275	1		T281	1
gen	zero	pass	mubi_false	1801	1			T4	1		T26	2		T15	1
gen	zero	pass	mubi_true	785	1			T7	2		T8	2		T24	1
res	non_zero_bins[0]	pass	mubi_false	193	1			T11	1		T21	2		T40	1
res	non_zero_bins[0]	pass	mubi_true	192	1			T3	2		T25	1		T23	2
res	non_zero_bins[1]	pass	mubi_false	136	1			T41	3		T76	1		T22	2
res	non_zero_bins[1]	pass	mubi_true	126	1			T11	3		T44	1		T41	6
res	zero	fail	mubi_false	1	1			T158	1		-	-		-	-
res	zero	pass	mubi_false	78	1			T54	1		T41	1		T76	1
res	zero	pass	mubi_true	87	1			T6	2		T76	1		T85	2
ins	non_zero_bins[0]	pass	mubi_false	502	1			T6	4		T23	1		T43	1
ins	non_zero_bins[0]	pass	mubi_true	508	1			T3	1		T24	1		T25	1
ins	non_zero_bins[1]	pass	mubi_false	336	1			T11	1		T6	1		T45	1
ins	non_zero_bins[1]	pass	mubi_true	348	1			T26	1		T6	1		T44	1
ins	zero	pass	mubi_false	2002	1			T7	1		T4	1		T26	1
ins	zero	pass	mubi_true	571	1			T7	1		T8	2		T11	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded