Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T8,T47,T89
1	1	Covered	T8,T24,T26

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T11,T5,T9
1	1	Covered	T3,T7,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T15
1	0	Covered	T4,T5,T34

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T7,T8,T15
1	Covered	T4,T5,T34

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T7,T8,T15
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T7,T8,T4
1	Covered	T4,T5,T34

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T3,T11,T15
AutoCaptGenCnt	143	Covered	T3,T11,T15
AutoCaptReseedCnt	141	Covered	T3,T11,T23
AutoDispatch	125	Covered	T3,T7,T11
AutoFirstAckWait	119	Covered	T3,T7,T11
AutoLoadIns	69	Covered	T3,T7,T11
AutoSendGenCmd	150	Covered	T3,T11,T15
AutoSendReseedCmd	162	Covered	T3,T11,T23
BootDone	98	Covered	T24,T26,T48
BootGenAckWait	90	Covered	T24,T26,T48
BootInsAckWait	80	Covered	T8,T24,T26
BootLoadGen	85	Covered	T8,T24,T26
BootLoadIns	65	Covered	T8,T24,T26
BootLoadUni	102	Covered	T24,T26,T43
BootPulse	94	Covered	T24,T26,T48
BootUniAckWait	107	Covered	T24,T26,T43
Error	188	Covered	T4,T5,T34
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T7,T8,T15
SWPortMode	74	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T3,T11,T23
AutoAckWait->Error	188	Covered	T115,T116,T117
AutoAckWait->Idle	211	Covered	T11,T118,T119
AutoAckWait->RejectCsrngEntropy	188	Covered	T15,T120,T121
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T3,T11,T15
AutoCaptGenCnt->Error	188	Covered	T17
AutoCaptGenCnt->Idle	211	Covered	T122,T123,T124
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T125,T126,T127
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T3,T11,T23
AutoCaptReseedCnt->Error	188	Covered	T128,T129,T130
AutoCaptReseedCnt->Idle	211	Covered	T131,T132,T133
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T134,T135,T136
AutoDispatch->AutoCaptGenCnt	143	Covered	T3,T11,T15
AutoDispatch->AutoCaptReseedCnt	141	Covered	T3,T11,T23
AutoDispatch->Error	188	Covered	T137
AutoDispatch->Idle	138	Covered	T3,T23,T21
AutoDispatch->RejectCsrngEntropy	188	Covered	T7,T138,T139
AutoFirstAckWait->AutoDispatch	125	Covered	T3,T7,T11
AutoFirstAckWait->Error	188	Covered	T9,T140,T141
AutoFirstAckWait->Idle	211	Covered	T142,T143,T144
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T51,T112,T145
AutoLoadIns->AutoFirstAckWait	119	Covered	T3,T7,T11
AutoLoadIns->Error	188	Covered	T5,T80,T146
AutoLoadIns->Idle	211	Covered	T7,T5,T51
AutoLoadIns->RejectCsrngEntropy	188	Covered	T47,T109,T100
AutoSendGenCmd->AutoAckWait	156	Covered	T3,T11,T15
AutoSendGenCmd->Error	188	Covered	T55,T147,T148
AutoSendGenCmd->Idle	211	Covered	T118,T149,T150
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T151,T152,T153
AutoSendReseedCmd->AutoAckWait	168	Covered	T3,T11,T23
AutoSendReseedCmd->Error	188	Covered	T58,T154,T155
AutoSendReseedCmd->Idle	211	Covered	T156,T69,T157
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T107,T111,T158
BootDone->BootLoadUni	102	Covered	T24,T26,T43
BootDone->Error	188	Covered	T59,T159,T160
BootDone->Idle	211	Covered	T161,T162,T163
BootDone->RejectCsrngEntropy	188	Covered	T48,T82,T108
BootGenAckWait->BootPulse	94	Covered	T24,T26,T48
BootGenAckWait->Error	188	Not Covered
BootGenAckWait->Idle	211	Covered	T164,T165,T166
BootGenAckWait->RejectCsrngEntropy	188	Covered	T87,T104,T167
BootInsAckWait->BootLoadGen	85	Covered	T8,T24,T26
BootInsAckWait->Error	188	Covered	T57,T61,T168
BootInsAckWait->Idle	211	Covered	T89,T169,T57
BootInsAckWait->RejectCsrngEntropy	188	Covered	T110,T170,T171
BootLoadGen->BootGenAckWait	90	Covered	T24,T26,T48
BootLoadGen->Error	188	Covered	T172,T173,T174
BootLoadGen->Idle	211	Covered	T175,T176,T177
BootLoadGen->RejectCsrngEntropy	188	Covered	T8,T178,T179
BootLoadIns->BootInsAckWait	80	Covered	T8,T24,T26
BootLoadIns->Error	188	Covered	T60,T180,T165
BootLoadIns->Idle	211	Covered	T102,T91,T95
BootLoadIns->RejectCsrngEntropy	188	Covered	T181,T182,T183
BootLoadUni->BootUniAckWait	107	Covered	T24,T26,T43
BootLoadUni->Error	188	Covered	T184,T185
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T186,T187,T188
BootPulse->BootDone	98	Covered	T24,T26,T48
BootPulse->Error	188	Covered	T189
BootPulse->Idle	211	Covered	T190,T191,T192
BootPulse->RejectCsrngEntropy	188	Covered	T193,T194,T195
BootUniAckWait->Error	188	Covered	T196,T197
BootUniAckWait->Idle	112	Covered	T24,T26,T43
BootUniAckWait->RejectCsrngEntropy	188	Covered	T83,T106,T88
Idle->AutoLoadIns	69	Covered	T3,T7,T11
Idle->BootLoadIns	65	Covered	T8,T24,T26
Idle->Error	188	Covered	T18,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T82,T83,T109
Idle->SWPortMode	74	Covered	T3,T7,T8
RejectCsrngEntropy->Error	188	Covered	T198,T199,T200
RejectCsrngEntropy->Idle	211	Covered	T7,T8,T15
SWPortMode->Error	188	Covered	T4,T16,T56
SWPortMode->Idle	211	Covered	T8,T15,T48
SWPortMode->RejectCsrngEntropy	188	Covered	T7,T8,T15

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T24,T26
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T24,T26
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T24,T26
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T8,T24,T26
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T24,T26
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T24,T26,T48
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T24,T26,T48
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T26,T48
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T26,T43
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T48,T89,T102
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T26,T43
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T24,T26,T43
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T24,T26,T43
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T7,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T7,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T7,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T7,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T23,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T11,T23
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T7,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T11,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T23
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T11,T23
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T11,T23
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T15
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T10,T81

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T5,T34
1	0	1	-	Not Covered
1	0	0	-	Covered	T7,T8,T15
0	-	-	1	Covered	T7,T8,T11
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	196914512	142621	0	0
FpvSecCmErrorStEscalate_A	196914512	143665	0	0
u_state_regs_A	196882574	196703540	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	142621	0	0
T4	755	348	0	0
T5	2223	1140	0	0
T6	31003	0	0	0
T9	0	273	0	0
T10	0	550	0	0
T15	2499	0	0	0
T16	0	391	0	0
T17	0	1092	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1038	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	756	0	0
T81	0	1113	0	0
T169	0	780	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	143665	0	0
T4	755	349	0	0
T5	2223	1141	0	0
T6	31003	0	0	0
T9	0	274	0	0
T10	0	551	0	0
T15	2499	0	0	0
T16	0	392	0	0
T17	0	1093	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1039	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	757	0	0
T81	0	1114	0	0
T169	0	781	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196882574	196703540	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	643	484	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0