Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T7,T8
DataWait	75	Covered	T3,T7,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T3,T7,T8
Error	99	Covered	T4,T5,T34
Idle	68	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T190,T192,T201
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T7,T8
DataWait->AckPls	80	Covered	T3,T7,T8
DataWait->Disabled	107	Covered	T89,T118,T122
DataWait->Error	99	Covered	T17,T81,T55
Disabled->EndPointClear	63	Covered	T3,T7,T8
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T102,T202,T91
EndPointClear->Error	99	Covered	T5,T169,T60
EndPointClear->Idle	68	Covered	T3,T7,T8
Idle->DataWait	75	Covered	T3,T7,T8
Idle->Disabled	107	Covered	T7,T8,T11
Idle->Error	99	Covered	T4,T34,T16

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T3,T7,T8
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T3,T7,T8
Idle	-	1	1	-	Covered	T3,T7,T8
Idle	-	1	0	-	Covered	T3,T7,T8
Idle	-	0	-	-	Covered	T3,T7,T8
DataWait	-	-	-	1	Covered	T3,T7,T8
DataWait	-	-	-	0	Covered	T3,T7,T8
AckPls	-	-	-	-	Covered	T3,T7,T8
Error	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	Covered	T4,T9,T80

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T34
0	1	Covered	T7,T8,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1378401584	1014447	0	0
FpvSecCmErrorStEscalate_A	1378401584	1021755	0	0
u_state_regs_A	1378369646	1377116408	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1378401584	1014447	0	0
T4	5285	2386	0	0
T5	15561	7980	0	0
T6	217021	0	0	0
T9	0	1861	0	0
T10	0	4200	0	0
T15	17493	0	0	0
T16	0	2737	0	0
T17	0	7644	0	0
T25	11641	0	0	0
T26	22764	0	0	0
T34	0	7616	0	0
T47	15113	0	0	0
T48	17206	0	0	0
T49	7623	0	0	0
T62	8715	0	0	0
T80	0	5242	0	0
T81	0	8141	0	0
T169	0	5810	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1378401584	1021755	0	0
T4	5285	2393	0	0
T5	15561	7987	0	0
T6	217021	0	0	0
T9	0	1868	0	0
T10	0	4207	0	0
T15	17493	0	0	0
T16	0	2744	0	0
T17	0	7651	0	0
T25	11641	0	0	0
T26	22764	0	0	0
T34	0	7623	0	0
T47	15113	0	0	0
T48	17206	0	0	0
T49	7623	0	0	0
T62	8715	0	0	0
T80	0	5249	0	0
T81	0	8148	0	0
T169	0	5817	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1378369646	1377116408	0	0
T1	11585	11165	0	0
T2	7042	6573	0	0
T3	46879	46242	0	0
T4	5173	4060	0	0
T7	19411	19033	0	0
T8	17290	16709	0	0
T11	13601	13230	0	0
T24	17276	16814	0	0
T25	11641	10976	0	0
T26	22764	22337	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T43,T44
DataWait	75	Covered	T24,T43,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T3,T7,T8
Error	99	Covered	T4,T5,T34
Idle	68	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T43,T44
DataWait->AckPls	80	Covered	T24,T43,T44
DataWait->Disabled	107	Covered	T203,T204,T124
DataWait->Error	99	Covered	T205,T206,T173
Disabled->EndPointClear	63	Covered	T3,T7,T8
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T102,T202,T91
EndPointClear->Error	99	Covered	T5,T169,T60
EndPointClear->Idle	68	Covered	T3,T7,T8
Idle->DataWait	75	Covered	T24,T43,T44
Idle->Disabled	107	Covered	T7,T8,T11
Idle->Error	99	Covered	T4,T34,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T3,T7,T8
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T3,T7,T8
Idle	-	1	1	-	Covered	T24,T43,T44
Idle	-	1	0	-	Covered	T24,T43,T44
Idle	-	0	-	-	Covered	T3,T7,T8
DataWait	-	-	-	1	Covered	T24,T43,T44
DataWait	-	-	-	0	Covered	T24,T43,T44
AckPls	-	-	-	-	Covered	T24,T43,T44
Error	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T34
0	1	Covered	T7,T8,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196914512	145221	0	0
FpvSecCmErrorStEscalate_A	196914512	146265	0	0
u_state_regs_A	196914512	196735478	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	145221	0	0
T4	755	348	0	0
T5	2223	1140	0	0
T6	31003	0	0	0
T9	0	273	0	0
T10	0	600	0	0
T15	2499	0	0	0
T16	0	391	0	0
T17	0	1092	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1088	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	756	0	0
T81	0	1163	0	0
T169	0	830	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	146265	0	0
T4	755	349	0	0
T5	2223	1141	0	0
T6	31003	0	0	0
T9	0	274	0	0
T10	0	601	0	0
T15	2499	0	0	0
T16	0	392	0	0
T17	0	1093	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1089	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	757	0	0
T81	0	1164	0	0
T169	0	831	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T43,T45,T46
DataWait	75	Covered	T43,T45,T46
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T3,T7,T8
Error	99	Covered	T4,T5,T34
Idle	68	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T43,T45,T46
DataWait->AckPls	80	Covered	T43,T45,T46
DataWait->Disabled	107	Covered	T207,T208,T209
DataWait->Error	99	Covered	T210,T211
Disabled->EndPointClear	63	Covered	T3,T7,T8
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T102,T202,T91
EndPointClear->Error	99	Covered	T5,T169,T60
EndPointClear->Idle	68	Covered	T3,T7,T8
Idle->DataWait	75	Covered	T43,T45,T46
Idle->Disabled	107	Covered	T7,T8,T11
Idle->Error	99	Covered	T4,T34,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T3,T7,T8
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T3,T7,T8
Idle	-	1	1	-	Covered	T43,T45,T46
Idle	-	1	0	-	Covered	T43,T45,T46
Idle	-	0	-	-	Covered	T3,T7,T8
DataWait	-	-	-	1	Covered	T43,T45,T46
DataWait	-	-	-	0	Covered	T43,T45,T46
AckPls	-	-	-	-	Covered	T43,T45,T46
Error	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T34
0	1	Covered	T7,T8,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196914512	145221	0	0
FpvSecCmErrorStEscalate_A	196914512	146265	0	0
u_state_regs_A	196914512	196735478	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	145221	0	0
T4	755	348	0	0
T5	2223	1140	0	0
T6	31003	0	0	0
T9	0	273	0	0
T10	0	600	0	0
T15	2499	0	0	0
T16	0	391	0	0
T17	0	1092	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1088	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	756	0	0
T81	0	1163	0	0
T169	0	830	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	146265	0	0
T4	755	349	0	0
T5	2223	1141	0	0
T6	31003	0	0	0
T9	0	274	0	0
T10	0	601	0	0
T15	2499	0	0	0
T16	0	392	0	0
T17	0	1093	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1089	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	757	0	0
T81	0	1164	0	0
T169	0	831	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T47,T43
DataWait	75	Covered	T3,T47,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T3,T7,T8
Error	99	Covered	T4,T5,T34
Idle	68	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T47,T43
DataWait->AckPls	80	Covered	T3,T47,T43
DataWait->Disabled	107	Covered	T177,T212,T213
DataWait->Error	99	Covered	T214,T215,T216
Disabled->EndPointClear	63	Covered	T3,T7,T8
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T102,T202,T91
EndPointClear->Error	99	Covered	T5,T169,T60
EndPointClear->Idle	68	Covered	T3,T7,T8
Idle->DataWait	75	Covered	T3,T47,T43
Idle->Disabled	107	Covered	T7,T8,T11
Idle->Error	99	Covered	T4,T34,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T3,T7,T8
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T3,T7,T8
Idle	-	1	1	-	Covered	T3,T47,T43
Idle	-	1	0	-	Covered	T3,T47,T43
Idle	-	0	-	-	Covered	T3,T7,T8
DataWait	-	-	-	1	Covered	T3,T47,T43
DataWait	-	-	-	0	Covered	T3,T47,T43
AckPls	-	-	-	-	Covered	T3,T47,T43
Error	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T34
0	1	Covered	T7,T8,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196914512	145221	0	0
FpvSecCmErrorStEscalate_A	196914512	146265	0	0
u_state_regs_A	196914512	196735478	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	145221	0	0
T4	755	348	0	0
T5	2223	1140	0	0
T6	31003	0	0	0
T9	0	273	0	0
T10	0	600	0	0
T15	2499	0	0	0
T16	0	391	0	0
T17	0	1092	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1088	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	756	0	0
T81	0	1163	0	0
T169	0	830	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	146265	0	0
T4	755	349	0	0
T5	2223	1141	0	0
T6	31003	0	0	0
T9	0	274	0	0
T10	0	601	0	0
T15	2499	0	0	0
T16	0	392	0	0
T17	0	1093	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1089	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	757	0	0
T81	0	1164	0	0
T169	0	831	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T25,T26
DataWait	75	Covered	T24,T25,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T3,T7,T8
Error	99	Covered	T4,T5,T34
Idle	68	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T201
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T25,T26
DataWait->AckPls	80	Covered	T24,T25,T26
DataWait->Disabled	107	Covered	T217,T218,T219
DataWait->Error	99	Covered	T17,T55,T59
Disabled->EndPointClear	63	Covered	T3,T7,T8
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T102,T202,T91
EndPointClear->Error	99	Covered	T5,T169,T60
EndPointClear->Idle	68	Covered	T3,T7,T8
Idle->DataWait	75	Covered	T24,T25,T26
Idle->Disabled	107	Covered	T7,T8,T11
Idle->Error	99	Covered	T34,T16,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T3,T7,T8
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T3,T7,T8
Idle	-	1	1	-	Covered	T24,T25,T26
Idle	-	1	0	-	Covered	T24,T25,T26
Idle	-	0	-	-	Covered	T3,T7,T8
DataWait	-	-	-	1	Covered	T24,T25,T26
DataWait	-	-	-	0	Covered	T24,T25,T26
AckPls	-	-	-	-	Covered	T24,T25,T26
Error	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	Covered	T4,T9,T80

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T34
0	1	Covered	T7,T8,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196914512	143121	0	0
FpvSecCmErrorStEscalate_A	196914512	144165	0	0
u_state_regs_A	196882574	196703540	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	143121	0	0
T4	755	298	0	0
T5	2223	1140	0	0
T6	31003	0	0	0
T9	0	223	0	0
T10	0	600	0	0
T15	2499	0	0	0
T16	0	391	0	0
T17	0	1092	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1088	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	706	0	0
T81	0	1163	0	0
T169	0	830	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	144165	0	0
T4	755	299	0	0
T5	2223	1141	0	0
T6	31003	0	0	0
T9	0	224	0	0
T10	0	601	0	0
T15	2499	0	0	0
T16	0	392	0	0
T17	0	1093	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1089	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	707	0	0
T81	0	1164	0	0
T169	0	831	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196882574	196703540	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	643	484	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T7,T8
DataWait	75	Covered	T3,T7,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T3,T7,T8
Error	99	Covered	T4,T5,T34
Idle	68	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T190
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T7,T8
DataWait->AckPls	80	Covered	T3,T7,T8
DataWait->Disabled	107	Covered	T118,T220,T221
DataWait->Error	99	Covered	T81,T147,T222
Disabled->EndPointClear	63	Covered	T3,T7,T8
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T102,T202,T91
EndPointClear->Error	99	Covered	T5,T169,T60
EndPointClear->Idle	68	Covered	T3,T7,T8
Idle->DataWait	75	Covered	T3,T7,T8
Idle->Disabled	107	Covered	T7,T8,T11
Idle->Error	99	Covered	T4,T34,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T3,T7,T8
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T3,T7,T8
Idle	-	1	1	-	Covered	T3,T7,T8
Idle	-	1	0	-	Covered	T3,T7,T8
Idle	-	0	-	-	Covered	T3,T7,T8
DataWait	-	-	-	1	Covered	T3,T7,T8
DataWait	-	-	-	0	Covered	T3,T7,T8
AckPls	-	-	-	-	Covered	T3,T7,T8
Error	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T34
0	1	Covered	T7,T8,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196914512	145221	0	0
FpvSecCmErrorStEscalate_A	196914512	146265	0	0
u_state_regs_A	196914512	196735478	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	145221	0	0
T4	755	348	0	0
T5	2223	1140	0	0
T6	31003	0	0	0
T9	0	273	0	0
T10	0	600	0	0
T15	2499	0	0	0
T16	0	391	0	0
T17	0	1092	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1088	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	756	0	0
T81	0	1163	0	0
T169	0	830	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	146265	0	0
T4	755	349	0	0
T5	2223	1141	0	0
T6	31003	0	0	0
T9	0	274	0	0
T10	0	601	0	0
T15	2499	0	0	0
T16	0	392	0	0
T17	0	1093	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1089	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	757	0	0
T81	0	1164	0	0
T169	0	831	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T11,T45
DataWait	75	Covered	T3,T11,T45
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T3,T7,T8
Error	99	Covered	T4,T5,T34
Idle	68	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T192
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T11,T45
DataWait->AckPls	80	Covered	T3,T11,T45
DataWait->Disabled	107	Covered	T175,T123,T223
DataWait->Error	99	Covered	T9,T115,T224
Disabled->EndPointClear	63	Covered	T3,T7,T8
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T102,T202,T91
EndPointClear->Error	99	Covered	T5,T169,T60
EndPointClear->Idle	68	Covered	T3,T7,T8
Idle->DataWait	75	Covered	T3,T11,T45
Idle->Disabled	107	Covered	T7,T8,T11
Idle->Error	99	Covered	T4,T34,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T3,T7,T8
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T3,T7,T8
Idle	-	1	1	-	Covered	T3,T11,T45
Idle	-	1	0	-	Covered	T3,T11,T45
Idle	-	0	-	-	Covered	T3,T7,T8
DataWait	-	-	-	1	Covered	T3,T11,T45
DataWait	-	-	-	0	Covered	T3,T11,T45
AckPls	-	-	-	-	Covered	T3,T11,T45
Error	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T34
0	1	Covered	T7,T8,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196914512	145221	0	0
FpvSecCmErrorStEscalate_A	196914512	146265	0	0
u_state_regs_A	196914512	196735478	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	145221	0	0
T4	755	348	0	0
T5	2223	1140	0	0
T6	31003	0	0	0
T9	0	273	0	0
T10	0	600	0	0
T15	2499	0	0	0
T16	0	391	0	0
T17	0	1092	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1088	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	756	0	0
T81	0	1163	0	0
T169	0	830	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	146265	0	0
T4	755	349	0	0
T5	2223	1141	0	0
T6	31003	0	0	0
T9	0	274	0	0
T10	0	601	0	0
T15	2499	0	0	0
T16	0	392	0	0
T17	0	1093	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1089	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	757	0	0
T81	0	1164	0	0
T169	0	831	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T4,T43
DataWait	75	Covered	T3,T4,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T3,T7,T8
Error	99	Covered	T4,T5,T34
Idle	68	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T225
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T4,T43
DataWait->AckPls	80	Covered	T3,T4,T43
DataWait->Disabled	107	Covered	T89,T122,T176
DataWait->Error	99	Covered	T57,T226,T160
Disabled->EndPointClear	63	Covered	T3,T7,T8
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T102,T202,T91
EndPointClear->Error	99	Covered	T5,T169,T60
EndPointClear->Idle	68	Covered	T3,T7,T8
Idle->DataWait	75	Covered	T3,T4,T43
Idle->Disabled	107	Covered	T7,T8,T11
Idle->Error	99	Covered	T4,T34,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T3,T7,T8
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T3,T7,T8
Idle	-	1	1	-	Covered	T3,T4,T43
Idle	-	1	0	-	Covered	T3,T4,T43
Idle	-	0	-	-	Covered	T3,T7,T8
DataWait	-	-	-	1	Covered	T3,T4,T43
DataWait	-	-	-	0	Covered	T3,T43,T51
AckPls	-	-	-	-	Covered	T3,T4,T43
Error	-	-	-	-	Covered	T4,T5,T34
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T34
0	1	Covered	T7,T8,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196914512	145221	0	0
FpvSecCmErrorStEscalate_A	196914512	146265	0	0
u_state_regs_A	196914512	196735478	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	145221	0	0
T4	755	348	0	0
T5	2223	1140	0	0
T6	31003	0	0	0
T9	0	273	0	0
T10	0	600	0	0
T15	2499	0	0	0
T16	0	391	0	0
T17	0	1092	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1088	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	756	0	0
T81	0	1163	0	0
T169	0	830	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	146265	0	0
T4	755	349	0	0
T5	2223	1141	0	0
T6	31003	0	0	0
T9	0	274	0	0
T10	0	601	0	0
T15	2499	0	0	0
T16	0	392	0	0
T17	0	1093	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T34	0	1089	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	757	0	0
T81	0	1164	0	0
T169	0	831	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0