Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T38,T39
1	0	1	Covered	T3,T7,T11
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T15

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393163704	1062542	0	0
DepthKnown_A	393829024	393470956	0	0
RvalidKnown_A	393829024	393470956	0	0
WreadyKnown_A	393829024	393470956	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	393522486	1143070	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393163704	1062542	0	0
T3	13394	10847	0	0
T4	400	0	0	0
T5	492	122	0	0
T7	5546	1038	0	0
T8	4940	0	0	0
T11	3886	2558	0	0
T15	4998	597	0	0
T21	0	4910	0	0
T23	0	10544	0	0
T24	4936	0	0	0
T25	3326	0	0	0
T26	6504	0	0	0
T47	0	332	0	0
T51	0	1143	0	0
T86	0	6027	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393829024	393470956	0	0
T1	3310	3190	0	0
T2	2012	1878	0	0
T3	13394	13212	0	0
T4	1510	1192	0	0
T7	5546	5438	0	0
T8	4940	4774	0	0
T11	3886	3780	0	0
T24	4936	4804	0	0
T25	3326	3136	0	0
T26	6504	6382	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393829024	393470956	0	0
T1	3310	3190	0	0
T2	2012	1878	0	0
T3	13394	13212	0	0
T4	1510	1192	0	0
T7	5546	5438	0	0
T8	4940	4774	0	0
T11	3886	3780	0	0
T24	4936	4804	0	0
T25	3326	3136	0	0
T26	6504	6382	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393829024	393470956	0	0
T1	3310	3190	0	0
T2	2012	1878	0	0
T3	13394	13212	0	0
T4	1510	1192	0	0
T7	5546	5438	0	0
T8	4940	4774	0	0
T11	3886	3780	0	0
T24	4936	4804	0	0
T25	3326	3136	0	0
T26	6504	6382	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	393522486	1143070	0	0
T3	13394	10847	0	0
T4	1510	0	0	0
T5	4446	1625	0	0
T7	5546	1038	0	0
T8	4940	0	0	0
T11	3886	2558	0	0
T15	4998	597	0	0
T21	0	4910	0	0
T23	0	10544	0	0
T24	4936	0	0	0
T25	3326	0	0	0
T26	6504	0	0	0
T47	0	332	0	0
T51	0	1143	0	0
T86	0	6027	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T99
1	0	1	Covered	T3,T7,T11
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	196581852	536889	0	0
DepthKnown_A	196914512	196735478	0	0
RvalidKnown_A	196914512	196735478	0	0
WreadyKnown_A	196914512	196735478	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	196761243	577501	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196581852	536889	0	0
T3	6697	5470	0	0
T4	200	0	0	0
T5	246	106	0	0
T7	2773	527	0	0
T8	2470	0	0	0
T11	1943	1292	0	0
T15	2499	295	0	0
T21	0	2472	0	0
T23	0	5322	0	0
T24	2468	0	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T47	0	160	0	0
T51	0	617	0	0
T86	0	3024	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	196761243	577501	0	0
T3	6697	5470	0	0
T4	755	0	0	0
T5	2223	872	0	0
T7	2773	527	0	0
T8	2470	0	0	0
T11	1943	1292	0	0
T15	2499	295	0	0
T21	0	2472	0	0
T23	0	5322	0	0
T24	2468	0	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T47	0	160	0	0
T51	0	617	0	0
T86	0	3024	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T80,T100
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T38,T39
1	0	1	Covered	T3,T7,T11
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	196581852	525653	0	0
DepthKnown_A	196914512	196735478	0	0
RvalidKnown_A	196914512	196735478	0	0
WreadyKnown_A	196914512	196735478	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	196761243	565569	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196581852	525653	0	0
T3	6697	5377	0	0
T4	200	0	0	0
T5	246	16	0	0
T7	2773	511	0	0
T8	2470	0	0	0
T11	1943	1266	0	0
T15	2499	302	0	0
T21	0	2438	0	0
T23	0	5222	0	0
T24	2468	0	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T47	0	172	0	0
T51	0	526	0	0
T86	0	3003	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	196761243	565569	0	0
T3	6697	5377	0	0
T4	755	0	0	0
T5	2223	753	0	0
T7	2773	511	0	0
T8	2470	0	0	0
T11	1943	1266	0	0
T15	2499	302	0	0
T21	0	2438	0	0
T23	0	5222	0	0
T24	2468	0	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T47	0	172	0	0
T51	0	526	0	0
T86	0	3003	0	0