Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	729243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6053954

1

T1

36

T2

33

T3

66

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1778394	1			T1	83		T2	75		T3	38
values[0x0]	2315057	1			T1	18		T2	21		T3	30
values[0x1]	2689746	1			T1	18		T2	13		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	356524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6426673

1

T1

56

T2

57

T3

79

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25977	1			T17	1		T15	1		T4	661
valid_sources[0x01]	27433	1			T15	2		T4	619		T36	1
valid_sources[0x02]	26867	1			T17	1		T22	1		T11	1
valid_sources[0x03]	28064	1			T4	633		T6	1		T44	1
valid_sources[0x04]	27562	1			T17	3		T15	1		T4	661
valid_sources[0x05]	26897	1			T4	623		T41	1		T21	2
valid_sources[0x06]	25870	1			T11	1		T15	1		T4	615
valid_sources[0x07]	26977	1			T11	1		T4	615		T35	21
valid_sources[0x08]	27871	1			T11	1		T15	1		T4	586
valid_sources[0x09]	27841	1			T22	1		T4	607		T36	1
valid_sources[0x0a]	26999	1			T23	1		T4	580		T36	1
valid_sources[0x0b]	26689	1			T2	1		T11	1		T4	656
valid_sources[0x0c]	25248	1			T2	1		T4	618		T33	373
valid_sources[0x0d]	27267	1			T2	2		T4	624		T36	6
valid_sources[0x0e]	24602	1			T4	622		T52	1		T33	362
valid_sources[0x0f]	25828	1			T2	1		T23	1		T4	616
valid_sources[0x10]	25689	1			T17	1		T22	4		T11	1
valid_sources[0x11]	28428	1			T2	1		T24	4		T4	627
valid_sources[0x12]	26471	1			T22	5		T24	1		T15	1
valid_sources[0x13]	24055	1			T11	1		T15	1		T4	630
valid_sources[0x14]	28475	1			T2	1		T17	1		T15	1
valid_sources[0x15]	27564	1			T10	2		T23	1		T11	1
valid_sources[0x16]	27766	1			T15	1		T4	544		T36	4
valid_sources[0x17]	25791	1			T2	1		T4	614		T36	2
valid_sources[0x18]	27081	1			T22	1		T15	1		T4	619
valid_sources[0x19]	26007	1			T22	2		T4	621		T52	1
valid_sources[0x1a]	28031	1			T4	615		T36	3		T44	1
valid_sources[0x1b]	25114	1			T4	620		T35	23		T36	4
valid_sources[0x1c]	26837	1			T22	4		T11	2		T4	577
valid_sources[0x1d]	26530	1			T17	1		T11	1		T24	4
valid_sources[0x1e]	24910	1			T4	586		T52	1		T21	3
valid_sources[0x1f]	27460	1			T2	1		T4	594		T36	3
valid_sources[0x20]	25271	1			T2	2		T4	592		T52	4
valid_sources[0x21]	27073	1			T11	2		T4	659		T52	1
valid_sources[0x22]	26544	1			T2	1		T4	631		T33	381
valid_sources[0x23]	26524	1			T2	1		T4	625		T36	2
valid_sources[0x24]	25467	1			T2	2		T17	3		T22	1
valid_sources[0x25]	27666	1			T22	2		T4	568		T33	375
valid_sources[0x26]	27242	1			T17	2		T11	1		T15	1
valid_sources[0x27]	28181	1			T4	640		T36	1		T41	2
valid_sources[0x28]	25996	1			T2	1		T22	4		T11	1
valid_sources[0x29]	26939	1			T2	1		T4	624		T36	2
valid_sources[0x2a]	27429	1			T4	593		T52	2		T21	2
valid_sources[0x2b]	24861	1			T2	2		T22	2		T4	575
valid_sources[0x2c]	24211	1			T11	2		T15	1		T4	569
valid_sources[0x2d]	25828	1			T17	1		T22	3		T4	611
valid_sources[0x2e]	27324	1			T15	1		T4	583		T36	4
valid_sources[0x2f]	25870	1			T4	612		T36	1		T7	2
valid_sources[0x30]	24848	1			T17	2		T23	1		T15	1
valid_sources[0x31]	26257	1			T4	650		T36	3		T7	1
valid_sources[0x32]	24698	1			T2	2		T17	4		T22	1
valid_sources[0x33]	28774	1			T22	2		T15	1		T4	604
valid_sources[0x34]	24902	1			T2	1		T22	2		T4	636
valid_sources[0x35]	26090	1			T22	5		T4	598		T52	2
valid_sources[0x36]	25108	1			T22	1		T15	2		T4	597
valid_sources[0x37]	25669	1			T2	2		T4	625		T41	1
valid_sources[0x38]	27290	1			T2	2		T10	7		T4	620
valid_sources[0x39]	25480	1			T22	1		T4	636		T36	6
valid_sources[0x3a]	29138	1			T22	1		T4	630		T36	1
valid_sources[0x3b]	26917	1			T4	583		T36	2		T44	2
valid_sources[0x3c]	26823	1			T2	2		T22	1		T24	1
valid_sources[0x3d]	26905	1			T4	606		T21	1		T33	388
valid_sources[0x3e]	25177	1			T4	621		T52	1		T36	3
valid_sources[0x3f]	27779	1			T2	1		T4	660		T21	1
valid_sources[0x40]	26074	1			T4	611		T36	3		T21	2
valid_sources[0x41]	23985	1			T10	7		T15	1		T4	635
valid_sources[0x42]	24892	1			T24	1		T4	604		T5	12
valid_sources[0x43]	25470	1			T15	1		T4	588		T33	373
valid_sources[0x44]	24873	1			T2	1		T15	1		T4	594
valid_sources[0x45]	27754	1			T2	1		T10	1		T22	2
valid_sources[0x46]	26535	1			T11	1		T15	1		T4	631
valid_sources[0x47]	26836	1			T22	1		T4	626		T52	4
valid_sources[0x48]	26665	1			T2	1		T4	584		T36	1
valid_sources[0x49]	26018	1			T2	1		T22	1		T4	625
valid_sources[0x4a]	25553	1			T22	2		T4	630		T52	1
valid_sources[0x4b]	25745	1			T2	1		T4	583		T36	3
valid_sources[0x4c]	25758	1			T17	2		T11	2		T24	1
valid_sources[0x4d]	27398	1			T2	1		T11	1		T15	1
valid_sources[0x4e]	25896	1			T24	1		T4	558		T52	2
valid_sources[0x4f]	25436	1			T2	1		T4	589		T36	5
valid_sources[0x50]	27834	1			T22	1		T23	1		T15	1
valid_sources[0x51]	24292	1			T15	1		T4	634		T52	2
valid_sources[0x52]	24098	1			T22	2		T15	1		T4	613
valid_sources[0x53]	26674	1			T11	2		T15	1		T4	603
valid_sources[0x54]	25367	1			T4	583		T33	385		T34	462
valid_sources[0x55]	26894	1			T4	624		T36	6		T33	379
valid_sources[0x56]	27094	1			T22	4		T15	4		T4	547
valid_sources[0x57]	25163	1			T4	604		T36	1		T33	438
valid_sources[0x58]	28466	1			T2	1		T4	590		T36	3
valid_sources[0x59]	24973	1			T17	1		T15	4		T4	636
valid_sources[0x5a]	25559	1			T2	1		T17	32		T4	646
valid_sources[0x5b]	26179	1			T11	1		T4	614		T52	1
valid_sources[0x5c]	25207	1			T17	1		T22	3		T4	610
valid_sources[0x5d]	27920	1			T24	6		T4	609		T36	1
valid_sources[0x5e]	27739	1			T22	2		T23	1		T4	600
valid_sources[0x5f]	26675	1			T23	2		T11	1		T24	1
valid_sources[0x60]	24744	1			T11	1		T4	626		T36	2
valid_sources[0x61]	26815	1			T4	615		T52	1		T36	1
valid_sources[0x62]	25287	1			T24	1		T4	616		T36	1
valid_sources[0x63]	27540	1			T2	1		T11	1		T4	630
valid_sources[0x64]	26364	1			T17	1		T24	1		T4	573
valid_sources[0x65]	26450	1			T15	1		T4	601		T36	5
valid_sources[0x66]	27208	1			T11	1		T24	1		T4	615
valid_sources[0x67]	26208	1			T4	628		T36	3		T21	1
valid_sources[0x68]	26579	1			T10	1		T15	2		T4	627
valid_sources[0x69]	26738	1			T2	1		T4	602		T36	1
valid_sources[0x6a]	26481	1			T2	1		T11	2		T4	602
valid_sources[0x6b]	27662	1			T2	2		T15	1		T4	626
valid_sources[0x6c]	26696	1			T2	2		T11	2		T15	1
valid_sources[0x6d]	29344	1			T17	1		T11	2		T4	539
valid_sources[0x6e]	26849	1			T2	2		T23	1		T11	1
valid_sources[0x6f]	26711	1			T4	590		T46	1		T33	384
valid_sources[0x70]	28573	1			T17	1		T4	614		T5	6
valid_sources[0x71]	25103	1			T24	3		T15	1		T4	627
valid_sources[0x72]	28292	1			T4	621		T36	4		T21	2
valid_sources[0x73]	25757	1			T4	588		T41	1		T7	1
valid_sources[0x74]	25288	1			T22	6		T4	647		T5	18
valid_sources[0x75]	27351	1			T23	1		T4	670		T36	7
valid_sources[0x76]	29046	1			T2	1		T4	625		T52	1
valid_sources[0x77]	28392	1			T2	2		T10	3		T11	2
valid_sources[0x78]	25174	1			T4	643		T36	1		T6	1
valid_sources[0x79]	27460	1			T22	4		T11	2		T4	629
valid_sources[0x7a]	25826	1			T11	1		T15	1		T4	605
valid_sources[0x7b]	24633	1			T22	1		T4	587		T7	1
valid_sources[0x7c]	26516	1			T15	1		T4	571		T52	1
valid_sources[0x7d]	27803	1			T24	1		T4	610		T36	3
valid_sources[0x7e]	27260	1			T4	625		T36	2		T44	1
valid_sources[0x7f]	26239	1			T2	2		T24	2		T4	604
valid_sources[0x80]	26038	1			T15	3		T4	656		T52	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1524343

1

T1

5

T2

3

T3

3

values[0x0]

all_enables

biggest_size

2267643

1

T1

16

T2

20

T3

26

values[0x1]

all_enables

biggest_size

2261968

1

T1

15

T2

10

T3

37