Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2659	1			T1	1		T2	1		T22	2
non_zero_bins[1]	1932	1			T1	2		T2	1		T3	5
zero	9379	1			T1	4		T2	6		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	546	1			T4	5		T33	9		T34	8
uni	3749	1			T1	2		T2	3		T3	1
gen	4351	1			T1	2		T2	2		T3	4
res	819	1			T1	1		T3	3		T11	1
ins	4505	1			T1	2		T2	3		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9233

1

T1

3

T2

8

T3

2

mubi_true

4737

1

T1

4

T3

7

T17

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

16

1

T38

1

T44

1

T268

1

pass

13954

1

T1

7

T2

8

T3

9

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	112	1			T4	2		T33	2		T34	3
upd	non_zero_bins[0]	pass	mubi_true	148	1			T4	1		T33	3		T34	2
upd	non_zero_bins[1]	pass	mubi_false	84	1			T33	2		T85	2		T214	2
upd	non_zero_bins[1]	pass	mubi_true	88	1			T34	1		T56	4		T85	2
upd	zero	pass	mubi_false	62	1			T4	2		T33	2		T56	1
upd	zero	pass	mubi_true	52	1			T34	2		T269	1		T85	1
uni	zero	pass	mubi_false	2804	1			T1	2		T2	3		T3	1
uni	zero	pass	mubi_true	945	1			T23	1		T4	13		T53	1
gen	non_zero_bins[0]	pass	mubi_false	497	1			T22	1		T15	1		T4	3
gen	non_zero_bins[0]	pass	mubi_true	460	1			T4	7		T41	1		T33	9
gen	non_zero_bins[1]	pass	mubi_false	397	1			T3	1		T15	3		T4	6
gen	non_zero_bins[1]	pass	mubi_true	355	1			T1	1		T4	5		T33	3
gen	zero	fail	mubi_false	15	1			T44	1		T268	1		T235	1
gen	zero	pass	mubi_false	1888	1			T2	2		T23	1		T11	1
gen	zero	pass	mubi_true	739	1			T1	1		T3	3		T17	2
res	non_zero_bins[0]	pass	mubi_false	173	1			T15	2		T4	1		T33	1
res	non_zero_bins[0]	pass	mubi_true	174	1			T1	1		T4	2		T33	2
res	non_zero_bins[1]	pass	mubi_false	135	1			T41	1		T21	2		T33	2
res	non_zero_bins[1]	pass	mubi_true	138	1			T3	3		T4	4		T36	1
res	zero	fail	mubi_false	1	1			T38	1		-	-		-	-
res	zero	pass	mubi_false	122	1			T11	1		T4	2		T73	1
res	zero	pass	mubi_true	76	1			T4	1		T37	1		T42	1
ins	non_zero_bins[0]	pass	mubi_false	560	1			T2	1		T22	1		T4	6
ins	non_zero_bins[0]	pass	mubi_true	535	1			T15	1		T4	8		T21	1
ins	non_zero_bins[1]	pass	mubi_false	358	1			T2	1		T4	6		T35	1
ins	non_zero_bins[1]	pass	mubi_true	377	1			T1	1		T3	1		T4	4
ins	zero	pass	mubi_false	2025	1			T1	1		T2	1		T10	1
ins	zero	pass	mubi_true	650	1			T17	1		T10	1		T11	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded