Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	769567	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6338068

1

T1

116

T2

73

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1869305	1			T1	291		T2	24		T3	1
values[0x0]	2423176	1			T1	12		T2	41		T3	8
values[0x1]	2815154	1			T1	11		T2	36		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	377530	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6730105

1

T1

173

T2

79

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27819	1			T2	1		T4	447		T41	911
valid_sources[0x01]	28842	1			T4	435		T25	1		T41	852
valid_sources[0x02]	28760	1			T1	2		T4	688		T41	867
valid_sources[0x03]	26359	1			T1	1		T22	2		T4	555
valid_sources[0x04]	28359	1			T22	3		T4	598		T25	1
valid_sources[0x05]	27269	1			T1	3		T4	604		T11	1
valid_sources[0x06]	27918	1			T1	2		T2	1		T4	494
valid_sources[0x07]	27175	1			T4	445		T41	839		T21	3
valid_sources[0x08]	26812	1			T2	3		T4	395		T11	1
valid_sources[0x09]	29311	1			T1	1		T4	495		T24	6
valid_sources[0x0a]	27259	1			T1	2		T22	4		T4	473
valid_sources[0x0b]	28673	1			T1	1		T4	622		T11	1
valid_sources[0x0c]	26878	1			T1	2		T4	624		T24	1
valid_sources[0x0d]	26254	1			T3	3		T22	1		T4	470
valid_sources[0x0e]	25914	1			T1	2		T4	609		T41	902
valid_sources[0x0f]	27629	1			T1	2		T2	1		T4	479
valid_sources[0x10]	27527	1			T1	3		T4	462		T60	3
valid_sources[0x11]	28838	1			T1	1		T4	586		T24	5
valid_sources[0x12]	27898	1			T4	350		T41	806		T42	732
valid_sources[0x13]	27696	1			T4	247		T10	9		T31	42
valid_sources[0x14]	27079	1			T1	1		T4	579		T25	1
valid_sources[0x15]	28276	1			T4	430		T29	1		T15	1
valid_sources[0x16]	27905	1			T22	1		T4	807		T10	1
valid_sources[0x17]	27366	1			T4	565		T19	75		T41	889
valid_sources[0x18]	27058	1			T1	3		T22	1		T4	444
valid_sources[0x19]	26561	1			T1	3		T2	1		T4	516
valid_sources[0x1a]	28869	1			T1	1		T3	1		T4	498
valid_sources[0x1b]	27881	1			T23	2		T4	626		T30	1
valid_sources[0x1c]	26923	1			T2	4		T4	563		T41	861
valid_sources[0x1d]	25572	1			T4	355		T29	3		T30	1
valid_sources[0x1e]	27556	1			T4	506		T30	2		T15	1
valid_sources[0x1f]	27231	1			T1	3		T22	2		T4	516
valid_sources[0x20]	29272	1			T22	2		T4	543		T11	2
valid_sources[0x21]	29155	1			T1	2		T4	748		T30	1
valid_sources[0x22]	27574	1			T1	3		T4	577		T29	1
valid_sources[0x23]	25670	1			T1	3		T22	4		T4	361
valid_sources[0x24]	26311	1			T2	4		T4	331		T41	859
valid_sources[0x25]	27046	1			T1	2		T4	579		T11	1
valid_sources[0x26]	28517	1			T22	2		T4	861		T24	1
valid_sources[0x27]	27563	1			T1	3		T2	1		T22	3
valid_sources[0x28]	26132	1			T1	1		T4	430		T11	1
valid_sources[0x29]	27275	1			T4	314		T60	17		T94	1
valid_sources[0x2a]	27416	1			T1	2		T2	2		T22	1
valid_sources[0x2b]	28830	1			T22	2		T4	674		T11	1
valid_sources[0x2c]	27699	1			T4	637		T24	1		T11	1
valid_sources[0x2d]	28893	1			T1	3		T4	623		T25	1
valid_sources[0x2e]	28972	1			T1	1		T4	629		T11	1
valid_sources[0x2f]	26649	1			T1	3		T2	2		T4	313
valid_sources[0x30]	27122	1			T1	1		T22	2		T4	357
valid_sources[0x31]	28260	1			T1	9		T22	1		T4	695
valid_sources[0x32]	25942	1			T4	406		T24	1		T11	3
valid_sources[0x33]	29298	1			T1	1		T4	488		T25	1
valid_sources[0x34]	26433	1			T4	465		T41	822		T21	1
valid_sources[0x35]	30501	1			T1	2		T22	1		T4	397
valid_sources[0x36]	27960	1			T1	2		T4	475		T30	1
valid_sources[0x37]	28292	1			T1	2		T4	501		T11	1
valid_sources[0x38]	27896	1			T1	2		T4	525		T10	1
valid_sources[0x39]	27151	1			T2	1		T4	582		T41	851
valid_sources[0x3a]	28574	1			T1	1		T4	635		T29	2
valid_sources[0x3b]	29460	1			T1	3		T4	543		T41	870
valid_sources[0x3c]	27435	1			T1	2		T2	1		T22	1
valid_sources[0x3d]	28905	1			T1	1		T22	1		T4	359
valid_sources[0x3e]	27393	1			T4	402		T11	1		T41	832
valid_sources[0x3f]	27313	1			T22	2		T4	385		T41	867
valid_sources[0x40]	29270	1			T4	407		T11	1		T31	1
valid_sources[0x41]	27666	1			T4	493		T11	1		T41	803
valid_sources[0x42]	28055	1			T1	2		T2	1		T23	1
valid_sources[0x43]	27101	1			T4	768		T11	1		T15	1
valid_sources[0x44]	31763	1			T1	1		T4	605		T24	2
valid_sources[0x45]	27455	1			T1	6		T4	496		T41	825
valid_sources[0x46]	26161	1			T1	2		T4	503		T25	1
valid_sources[0x47]	27976	1			T22	2		T4	365		T31	3
valid_sources[0x48]	27348	1			T22	1		T4	738		T41	795
valid_sources[0x49]	26988	1			T1	5		T3	2		T4	670
valid_sources[0x4a]	26922	1			T1	2		T4	500		T11	2
valid_sources[0x4b]	27371	1			T1	6		T2	1		T4	497
valid_sources[0x4c]	28588	1			T4	455		T11	1		T41	847
valid_sources[0x4d]	28189	1			T2	1		T4	762		T43	1
valid_sources[0x4e]	29992	1			T2	3		T4	561		T10	5
valid_sources[0x4f]	25330	1			T4	407		T41	873		T21	2
valid_sources[0x50]	27627	1			T1	1		T22	1		T4	595
valid_sources[0x51]	28054	1			T4	587		T11	1		T94	2
valid_sources[0x52]	26772	1			T1	1		T4	401		T25	1
valid_sources[0x53]	28211	1			T2	1		T4	540		T11	1
valid_sources[0x54]	28087	1			T4	234		T11	1		T29	4
valid_sources[0x55]	27936	1			T1	2		T4	479		T59	11
valid_sources[0x56]	26205	1			T2	1		T22	5		T4	451
valid_sources[0x57]	28454	1			T4	557		T24	1		T60	4
valid_sources[0x58]	28139	1			T1	2		T4	534		T10	2
valid_sources[0x59]	27653	1			T4	550		T10	5		T30	2
valid_sources[0x5a]	27052	1			T1	3		T4	448		T11	1
valid_sources[0x5b]	27432	1			T4	567		T29	1		T15	1
valid_sources[0x5c]	27856	1			T2	1		T4	607		T41	829
valid_sources[0x5d]	26937	1			T4	475		T11	1		T41	855
valid_sources[0x5e]	28321	1			T4	524		T15	2		T20	5
valid_sources[0x5f]	27495	1			T1	2		T2	1		T4	538
valid_sources[0x60]	27992	1			T2	1		T22	1		T4	464
valid_sources[0x61]	27641	1			T1	3		T4	342		T11	1
valid_sources[0x62]	26501	1			T1	5		T22	1		T4	417
valid_sources[0x63]	25566	1			T4	360		T10	2		T29	1
valid_sources[0x64]	29911	1			T2	1		T4	319		T11	1
valid_sources[0x65]	29570	1			T1	1		T4	617		T29	2
valid_sources[0x66]	29645	1			T1	4		T4	572		T29	1
valid_sources[0x67]	27565	1			T4	596		T41	842		T21	1
valid_sources[0x68]	26800	1			T1	2		T4	694		T11	1
valid_sources[0x69]	28212	1			T1	2		T4	454		T30	1
valid_sources[0x6a]	29753	1			T1	4		T4	605		T29	1
valid_sources[0x6b]	26978	1			T4	553		T10	4		T11	1
valid_sources[0x6c]	27548	1			T1	1		T4	867		T25	1
valid_sources[0x6d]	30642	1			T1	1		T2	3		T22	2
valid_sources[0x6e]	27770	1			T1	1		T4	569		T25	1
valid_sources[0x6f]	28107	1			T1	1		T4	634		T11	1
valid_sources[0x70]	28048	1			T4	632		T29	2		T30	1
valid_sources[0x71]	26079	1			T4	277		T11	1		T94	1
valid_sources[0x72]	27531	1			T1	1		T2	3		T22	1
valid_sources[0x73]	26385	1			T22	1		T4	225		T11	1
valid_sources[0x74]	28577	1			T1	4		T3	3		T4	653
valid_sources[0x75]	25871	1			T4	459		T41	783		T48	1
valid_sources[0x76]	27336	1			T1	1		T2	1		T4	566
valid_sources[0x77]	28901	1			T1	2		T4	469		T29	1
valid_sources[0x78]	27989	1			T1	1		T22	1		T4	676
valid_sources[0x79]	26131	1			T4	495		T24	2		T11	1
valid_sources[0x7a]	28594	1			T1	3		T2	1		T4	464
valid_sources[0x7b]	28515	1			T1	6		T22	1		T4	647
valid_sources[0x7c]	27089	1			T22	1		T4	397		T41	875
valid_sources[0x7d]	26870	1			T1	1		T2	1		T4	379
valid_sources[0x7e]	27978	1			T4	536		T11	1		T41	833
valid_sources[0x7f]	26369	1			T1	1		T2	1		T4	460
valid_sources[0x80]	28360	1			T1	2		T2	1		T4	559

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1594290

1

T1

106

T2

3

T3

1

values[0x0]

all_enables

biggest_size

2374167

1

T1

7

T2

37

T3

2

values[0x1]

all_enables

biggest_size

2369611

1

T1

3

T2

33

T3

2