Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2857	1			T2	2		T6	1		T22	2
non_zero_bins[1]	2097	1			T2	3		T6	2		T22	1
zero	10080	1			T2	4		T6	4		T22	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	579	1			T4	10		T29	1		T41	16
uni	4022	1			T6	2		T22	1		T4	86
gen	4721	1			T2	3		T6	2		T22	1
res	916	1			T2	4		T6	1		T22	1
ins	4796	1			T2	2		T6	2		T22	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

10001

1

T6

3

T22

3

T4

205

mubi_true

5033

1

T2

9

T6

4

T22

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

19

1

T47

1

T135

1

T147

1

pass

15015

1

T2

9

T6

7

T22

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	141	1			T4	1		T41	7		T42	2
upd	non_zero_bins[0]	pass	mubi_true	121	1			T41	3		T42	3		T223	1
upd	non_zero_bins[1]	pass	mubi_false	90	1			T41	3		T42	3		T81	2
upd	non_zero_bins[1]	pass	mubi_true	96	1			T4	3		T41	2		T42	3
upd	zero	pass	mubi_false	59	1			T4	5		T29	1		T207	1
upd	zero	pass	mubi_true	72	1			T4	1		T41	1		T81	2
uni	zero	pass	mubi_false	2983	1			T6	2		T22	1		T4	61
uni	zero	pass	mubi_true	1039	1			T4	25		T41	17		T42	27
gen	non_zero_bins[0]	pass	mubi_false	559	1			T6	1		T4	9		T11	1
gen	non_zero_bins[0]	pass	mubi_true	511	1			T4	8		T10	3		T60	1
gen	non_zero_bins[1]	pass	mubi_false	388	1			T22	1		T4	9		T11	3
gen	non_zero_bins[1]	pass	mubi_true	422	1			T2	3		T4	4		T41	4
gen	zero	fail	mubi_false	15	1			T47	1		T147	1		T257	1
gen	zero	pass	mubi_false	2076	1			T4	48		T10	1		T25	1
gen	zero	pass	mubi_true	750	1			T6	1		T4	1		T29	2
res	non_zero_bins[0]	pass	mubi_false	197	1			T4	4		T11	2		T19	2
res	non_zero_bins[0]	pass	mubi_true	206	1			T22	1		T4	9		T41	5
res	non_zero_bins[1]	pass	mubi_false	140	1			T41	1		T42	4		T81	1
res	non_zero_bins[1]	pass	mubi_true	160	1			T6	1		T4	3		T10	2
res	zero	fail	mubi_false	4	1			T135	1		T136	1		T137	1
res	zero	pass	mubi_false	112	1			T41	1		T42	2		T81	3
res	zero	pass	mubi_true	97	1			T2	4		T4	1		T41	1
ins	non_zero_bins[0]	pass	mubi_false	560	1			T22	1		T4	8		T60	1
ins	non_zero_bins[0]	pass	mubi_true	562	1			T2	2		T4	7		T41	7
ins	non_zero_bins[1]	pass	mubi_false	413	1			T4	6		T41	9		T42	10
ins	non_zero_bins[1]	pass	mubi_true	388	1			T6	1		T4	4		T29	1
ins	zero	pass	mubi_false	2264	1			T4	54		T25	1		T59	1
ins	zero	pass	mubi_true	609	1			T6	1		T4	7		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded