Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T30,T15,T43
1	1	Covered	T6,T29,T30

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T22
1	0	Covered	T2,T58,T7
1	1	Covered	T2,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T1,T5,T15

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T30,T31,T32
1	Covered	T1,T5,T15

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T30,T31,T32
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T5,T30
1	Covered	T1,T5,T15

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T10,T11
AutoCaptGenCnt	143	Covered	T2,T10,T11
AutoCaptReseedCnt	141	Covered	T2,T10,T11
AutoDispatch	125	Covered	T2,T10,T11
AutoFirstAckWait	119	Covered	T2,T10,T11
AutoLoadIns	69	Covered	T2,T10,T11
AutoSendGenCmd	150	Covered	T2,T10,T11
AutoSendReseedCmd	162	Covered	T2,T10,T11
BootDone	98	Covered	T6,T29,T30
BootGenAckWait	90	Covered	T6,T29,T30
BootInsAckWait	80	Covered	T6,T29,T30
BootLoadGen	85	Covered	T6,T29,T30
BootLoadIns	65	Covered	T6,T29,T30
BootLoadUni	102	Covered	T6,T29,T30
BootPulse	94	Covered	T6,T29,T30
BootUniAckWait	107	Covered	T6,T29,T30
Error	188	Covered	T1,T5,T15
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T30,T31,T32
SWPortMode	74	Covered	T1,T6,T22

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T10,T11
AutoAckWait->Error	188	Covered	T95
AutoAckWait->Idle	211	Covered	T2,T58,T96
AutoAckWait->RejectCsrngEntropy	188	Covered	T47,T63,T97
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T10,T11
AutoCaptGenCnt->Error	188	Covered	T98,T99,T100
AutoCaptGenCnt->Idle	211	Covered	T101,T102,T103
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T76,T83,T104
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T10,T11
AutoCaptReseedCnt->Error	188	Covered	T105,T106,T107
AutoCaptReseedCnt->Idle	211	Covered	T2,T108,T109
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T110,T111,T112
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T10,T11
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T10,T11
AutoDispatch->Error	188	Covered	T113
AutoDispatch->Idle	138	Covered	T10,T11,T19
AutoDispatch->RejectCsrngEntropy	188	Covered	T82,T114,T115
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T10,T11
AutoFirstAckWait->Error	188	Covered	T116,T117
AutoFirstAckWait->Idle	211	Covered	T96,T118,T119
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T120,T121,T122
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T10,T11
AutoLoadIns->Error	188	Covered	T123,T124
AutoLoadIns->Idle	211	Covered	T31,T32,T7
AutoLoadIns->RejectCsrngEntropy	188	Covered	T86,T125,T126
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T10,T11
AutoSendGenCmd->Error	188	Covered	T87
AutoSendGenCmd->Idle	211	Covered	T58,T127,T128
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T129,T88,T130
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T10,T11
AutoSendReseedCmd->Error	188	Covered	T131,T132
AutoSendReseedCmd->Idle	211	Covered	T73,T133,T134
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T135,T136,T137
BootDone->BootLoadUni	102	Covered	T6,T29,T30
BootDone->Error	188	Covered	T52,T138,T139
BootDone->Idle	211	Covered	T68,T140,T141
BootDone->RejectCsrngEntropy	188	Covered	T31,T32,T84
BootGenAckWait->BootPulse	94	Covered	T6,T29,T30
BootGenAckWait->Error	188	Covered	T142,T143
BootGenAckWait->Idle	211	Covered	T144,T54,T145
BootGenAckWait->RejectCsrngEntropy	188	Covered	T146,T147,T148
BootInsAckWait->BootLoadGen	85	Covered	T6,T29,T30
BootInsAckWait->Error	188	Covered	T50,T149,T150
BootInsAckWait->Idle	211	Covered	T15,T48,T78
BootInsAckWait->RejectCsrngEntropy	188	Covered	T62,T90,T72
BootLoadGen->BootGenAckWait	90	Covered	T6,T29,T30
BootLoadGen->Error	188	Covered	T151,T152
BootLoadGen->Idle	211	Covered	T67,T153,T154
BootLoadGen->RejectCsrngEntropy	188	Covered	T155,T156,T157
BootLoadIns->BootInsAckWait	80	Covered	T6,T29,T30
BootLoadIns->Error	188	Covered	T48,T158,T159
BootLoadIns->Idle	211	Covered	T160,T161,T162
BootLoadIns->RejectCsrngEntropy	188	Covered	T163,T164,T165
BootLoadUni->BootUniAckWait	107	Covered	T6,T29,T30
BootLoadUni->Error	188	Covered	T15,T78,T144
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T166,T167,T168
BootPulse->BootDone	98	Covered	T6,T29,T30
BootPulse->Error	188	Covered	T169,T170,T171
BootPulse->Idle	211	Covered	T43,T172,T173
BootPulse->RejectCsrngEntropy	188	Covered	T85,T174,T175
BootUniAckWait->Error	188	Covered	T53,T176
BootUniAckWait->Idle	112	Covered	T6,T29,T44
BootUniAckWait->RejectCsrngEntropy	188	Covered	T30,T177,T178
Idle->AutoLoadIns	69	Covered	T2,T10,T11
Idle->BootLoadIns	65	Covered	T6,T29,T30
Idle->Error	188	Covered	T1,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T30,T32,T76
Idle->SWPortMode	74	Covered	T1,T6,T22
RejectCsrngEntropy->Error	188	Not Covered
RejectCsrngEntropy->Idle	211	Covered	T30,T31,T32
SWPortMode->Error	188	Covered	T1,T5,T16
SWPortMode->Idle	211	Covered	T1,T4,T30
SWPortMode->RejectCsrngEntropy	188	Covered	T31,T47,T63

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T22
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T15,T31,T43
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T6,T29,T30
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T29,T30
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T11,T19
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T10,T11
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T10,T11
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T22
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T31,T32
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T5,T15
1	0	1	-	Not Covered
1	0	0	-	Covered	T30,T31,T32
0	-	-	1	Covered	T2,T30,T15
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	243501794	156614	0	0
FpvSecCmErrorStEscalate_A	243501794	157788	0	0
u_state_regs_A	243464504	243276046	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	156614	0	0
T1	23049	8463	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1068	0	0
T6	5534	0	0	0
T7	0	660	0	0
T8	0	917	0	0
T10	1412	0	0	0
T15	0	669	0	0
T16	0	1117	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1106	0	0
T49	0	386	0	0
T78	0	410	0	0
T144	0	1145	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	157788	0	0
T1	23049	8593	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1069	0	0
T6	5534	0	0	0
T7	0	661	0	0
T8	0	918	0	0
T10	1412	0	0	0
T15	0	670	0	0
T16	0	1118	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1107	0	0
T49	0	387	0	0
T78	0	411	0	0
T144	0	1146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243464504	243276046	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0