Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T22,T4
DataWait	75	Covered	T6,T22,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T1,T5,T15
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T173,T179,T180
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T22,T4
DataWait->AckPls	80	Covered	T6,T22,T4
DataWait->Disabled	107	Covered	T67,T58,T153
DataWait->Error	99	Covered	T15,T7,T144
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T1,T17,T18
EndPointClear->Disabled	107	Covered	T160,T161,T181
EndPointClear->Error	99	Covered	T1,T48,T158
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T22,T4
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T22,T4
Idle	-	1	0	-	Covered	T6,T22,T4
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T22,T4
DataWait	-	-	-	0	Covered	T6,T22,T4
AckPls	-	-	-	-	Covered	T6,T22,T4
Error	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	Covered	T1,T5,T78

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T2,T30,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1704512558	1113198	0	0
FpvSecCmErrorStEscalate_A	1704512558	1121416	0	0
u_state_regs_A	1704475268	1703156062	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1704512558	1113198	0	0
T1	161343	59241	0	0
T2	20083	0	0	0
T3	7630	0	0	0
T4	4234517	0	0	0
T5	0	7426	0	0
T6	38738	0	0	0
T7	0	4970	0	0
T8	0	6769	0	0
T10	9884	0	0	0
T15	0	4683	0	0
T16	0	7819	0	0
T22	17815	0	0	0
T23	7084	0	0	0
T24	11753	0	0	0
T25	8687	0	0	0
T48	0	7742	0	0
T49	0	2702	0	0
T78	0	2820	0	0
T144	0	7965	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1704512558	1121416	0	0
T1	161343	60151	0	0
T2	20083	0	0	0
T3	7630	0	0	0
T4	4234517	0	0	0
T5	0	7433	0	0
T6	38738	0	0	0
T7	0	4977	0	0
T8	0	6776	0	0
T10	9884	0	0	0
T15	0	4690	0	0
T16	0	7826	0	0
T22	17815	0	0	0
T23	7084	0	0	0
T24	11753	0	0	0
T25	8687	0	0	0
T48	0	7749	0	0
T49	0	2709	0	0
T78	0	2827	0	0
T144	0	7972	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1704475268	1703156062	0	0
T1	161343	87752	0	0
T2	20083	19726	0	0
T3	7630	7224	0	0
T4	4234517	4234440	0	0
T6	38738	38192	0	0
T10	9884	9261	0	0
T22	17815	17199	0	0
T23	7084	6482	0	0
T24	11753	11403	0	0
T25	8687	8029	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T22,T20
DataWait	75	Covered	T6,T22,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T1,T5,T15
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T22,T20
DataWait->AckPls	80	Covered	T6,T22,T20
DataWait->Disabled	107	Covered	T182,T183,T101
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T1,T17,T18
EndPointClear->Disabled	107	Covered	T160,T161,T181
EndPointClear->Error	99	Covered	T1,T48,T158
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T22,T20
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T22,T20
Idle	-	1	0	-	Covered	T6,T22,T20
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T22,T20
DataWait	-	-	-	0	Covered	T6,T22,T20
AckPls	-	-	-	-	Covered	T6,T22,T20
Error	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	Covered	T1,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T2,T30,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243501794	159314	0	0
FpvSecCmErrorStEscalate_A	243501794	160488	0	0
u_state_regs_A	243501794	243313336	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	159314	0	0
T1	23049	8463	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1068	0	0
T6	5534	0	0	0
T7	0	710	0	0
T8	0	967	0	0
T10	1412	0	0	0
T15	0	669	0	0
T16	0	1117	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1106	0	0
T49	0	386	0	0
T78	0	410	0	0
T144	0	1145	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	160488	0	0
T1	23049	8593	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1069	0	0
T6	5534	0	0	0
T7	0	711	0	0
T8	0	968	0	0
T10	1412	0	0	0
T15	0	670	0	0
T16	0	1118	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1107	0	0
T49	0	387	0	0
T78	0	411	0	0
T144	0	1146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T29,T20
DataWait	75	Covered	T22,T29,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T1,T5,T15
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T29,T20
DataWait->AckPls	80	Covered	T22,T29,T20
DataWait->Disabled	107	Covered	T102,T184,T185
DataWait->Error	99	Covered	T176,T186
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T1,T17,T18
EndPointClear->Disabled	107	Covered	T160,T161,T181
EndPointClear->Error	99	Covered	T1,T48,T158
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T22,T29,T20
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T22,T29,T20
Idle	-	1	0	-	Covered	T22,T29,T20
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T22,T29,T20
DataWait	-	-	-	0	Covered	T22,T29,T20
AckPls	-	-	-	-	Covered	T22,T29,T20
Error	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	Covered	T1,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T2,T30,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243501794	159314	0	0
FpvSecCmErrorStEscalate_A	243501794	160488	0	0
u_state_regs_A	243501794	243313336	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	159314	0	0
T1	23049	8463	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1068	0	0
T6	5534	0	0	0
T7	0	710	0	0
T8	0	967	0	0
T10	1412	0	0	0
T15	0	669	0	0
T16	0	1117	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1106	0	0
T49	0	386	0	0
T78	0	410	0	0
T144	0	1145	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	160488	0	0
T1	23049	8593	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1069	0	0
T6	5534	0	0	0
T7	0	711	0	0
T8	0	968	0	0
T10	1412	0	0	0
T15	0	670	0	0
T16	0	1118	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1107	0	0
T49	0	387	0	0
T78	0	411	0	0
T144	0	1146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T20,T21
DataWait	75	Covered	T2,T20,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T1,T5,T15
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T20,T21
DataWait->AckPls	80	Covered	T2,T20,T21
DataWait->Disabled	107	Covered	T67,T154,T187
DataWait->Error	99	Covered	T144,T188,T116
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T1,T17,T18
EndPointClear->Disabled	107	Covered	T160,T161,T181
EndPointClear->Error	99	Covered	T1,T48,T158
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T2,T20,T21
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T2,T20,T21
Idle	-	1	0	-	Covered	T2,T20,T21
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T2,T20,T21
DataWait	-	-	-	0	Covered	T2,T20,T21
AckPls	-	-	-	-	Covered	T2,T20,T21
Error	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	Covered	T1,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T2,T30,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243501794	159314	0	0
FpvSecCmErrorStEscalate_A	243501794	160488	0	0
u_state_regs_A	243501794	243313336	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	159314	0	0
T1	23049	8463	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1068	0	0
T6	5534	0	0	0
T7	0	710	0	0
T8	0	967	0	0
T10	1412	0	0	0
T15	0	669	0	0
T16	0	1117	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1106	0	0
T49	0	386	0	0
T78	0	410	0	0
T144	0	1145	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	160488	0	0
T1	23049	8593	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1069	0	0
T6	5534	0	0	0
T7	0	711	0	0
T8	0	968	0	0
T10	1412	0	0	0
T15	0	670	0	0
T16	0	1118	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1107	0	0
T49	0	387	0	0
T78	0	411	0	0
T144	0	1146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T43,T21
DataWait	75	Covered	T22,T43,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T1,T5,T15
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T43,T21
DataWait->AckPls	80	Covered	T22,T43,T21
DataWait->Disabled	107	Covered	T127,T189
DataWait->Error	99	Covered	T190
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T1,T17,T18
EndPointClear->Disabled	107	Covered	T160,T161,T181
EndPointClear->Error	99	Covered	T1,T48,T158
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T22,T43,T21
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T22,T43,T21
Idle	-	1	0	-	Covered	T22,T43,T21
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T22,T43,T21
DataWait	-	-	-	0	Covered	T22,T43,T21
AckPls	-	-	-	-	Covered	T22,T43,T21
Error	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	Covered	T1,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T2,T30,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243501794	159314	0	0
FpvSecCmErrorStEscalate_A	243501794	160488	0	0
u_state_regs_A	243501794	243313336	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	159314	0	0
T1	23049	8463	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1068	0	0
T6	5534	0	0	0
T7	0	710	0	0
T8	0	967	0	0
T10	1412	0	0	0
T15	0	669	0	0
T16	0	1117	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1106	0	0
T49	0	386	0	0
T78	0	410	0	0
T144	0	1145	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	160488	0	0
T1	23049	8593	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1069	0	0
T6	5534	0	0	0
T7	0	711	0	0
T8	0	968	0	0
T10	1412	0	0	0
T15	0	670	0	0
T16	0	1118	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1107	0	0
T49	0	387	0	0
T78	0	411	0	0
T144	0	1146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T22,T4
DataWait	75	Covered	T6,T22,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T1,T5,T15
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T180
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T22,T4
DataWait->AckPls	80	Covered	T6,T22,T4
DataWait->Disabled	107	Covered	T58,T191,T192
DataWait->Error	99	Covered	T15,T9,T193
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T1,T17,T18
EndPointClear->Disabled	107	Covered	T160,T161,T181
EndPointClear->Error	99	Covered	T1,T48,T159
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T22,T4
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T16,T49,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T22,T4
Idle	-	1	0	-	Covered	T6,T22,T4
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T22,T4
DataWait	-	-	-	0	Covered	T6,T22,T4
AckPls	-	-	-	-	Covered	T6,T22,T4
Error	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	Covered	T1,T5,T78

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T2,T30,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243501794	157314	0	0
FpvSecCmErrorStEscalate_A	243501794	158488	0	0
u_state_regs_A	243464504	243276046	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	157314	0	0
T1	23049	8463	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1018	0	0
T6	5534	0	0	0
T7	0	710	0	0
T8	0	967	0	0
T10	1412	0	0	0
T15	0	669	0	0
T16	0	1117	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1106	0	0
T49	0	386	0	0
T78	0	360	0	0
T144	0	1095	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	158488	0	0
T1	23049	8593	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1019	0	0
T6	5534	0	0	0
T7	0	711	0	0
T8	0	968	0	0
T10	1412	0	0	0
T15	0	670	0	0
T16	0	1118	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1107	0	0
T49	0	387	0	0
T78	0	361	0	0
T144	0	1096	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243464504	243276046	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T22,T20
DataWait	75	Covered	T6,T22,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T1,T5,T15
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T173
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T22,T20
DataWait->AckPls	80	Covered	T6,T22,T20
DataWait->Disabled	107	Covered	T153,T194,T195
DataWait->Error	99	Covered	T7,T151,T145
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T1,T17,T18
EndPointClear->Disabled	107	Covered	T160,T161,T181
EndPointClear->Error	99	Covered	T1,T48,T158
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T22,T20
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T22,T20
Idle	-	1	0	-	Covered	T6,T22,T20
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T22,T20
DataWait	-	-	-	0	Covered	T6,T22,T20
AckPls	-	-	-	-	Covered	T6,T22,T20
Error	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	Covered	T1,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T2,T30,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243501794	159314	0	0
FpvSecCmErrorStEscalate_A	243501794	160488	0	0
u_state_regs_A	243501794	243313336	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	159314	0	0
T1	23049	8463	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1068	0	0
T6	5534	0	0	0
T7	0	710	0	0
T8	0	967	0	0
T10	1412	0	0	0
T15	0	669	0	0
T16	0	1117	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1106	0	0
T49	0	386	0	0
T78	0	410	0	0
T144	0	1145	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	160488	0	0
T1	23049	8593	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1069	0	0
T6	5534	0	0	0
T7	0	711	0	0
T8	0	968	0	0
T10	1412	0	0	0
T15	0	670	0	0
T16	0	1118	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1107	0	0
T49	0	387	0	0
T78	0	411	0	0
T144	0	1146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T30,T15

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T21,T44
DataWait	75	Covered	T22,T21,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T1,T5,T15
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T179
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T21,T44
DataWait->AckPls	80	Covered	T22,T21,T44
DataWait->Disabled	107	Covered	T196
DataWait->Error	99	Covered	T8,T87,T170
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T1,T17,T18
EndPointClear->Disabled	107	Covered	T160,T161,T181
EndPointClear->Error	99	Covered	T1,T48,T158
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T22,T21,T44
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T22,T21,T44
Idle	-	1	0	-	Covered	T22,T21,T44
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T22,T21,T44
DataWait	-	-	-	0	Covered	T22,T21,T44
AckPls	-	-	-	-	Covered	T22,T21,T44
Error	-	-	-	-	Covered	T1,T5,T15
default	-	-	-	-	Covered	T1,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T2,T30,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243501794	159314	0	0
FpvSecCmErrorStEscalate_A	243501794	160488	0	0
u_state_regs_A	243501794	243313336	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	159314	0	0
T1	23049	8463	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1068	0	0
T6	5534	0	0	0
T7	0	710	0	0
T8	0	967	0	0
T10	1412	0	0	0
T15	0	669	0	0
T16	0	1117	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1106	0	0
T49	0	386	0	0
T78	0	410	0	0
T144	0	1145	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	160488	0	0
T1	23049	8593	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1069	0	0
T6	5534	0	0	0
T7	0	711	0	0
T8	0	968	0	0
T10	1412	0	0	0
T15	0	670	0	0
T16	0	1118	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1107	0	0
T49	0	387	0	0
T78	0	411	0	0
T144	0	1146	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0