Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36,T37,T75
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T39,T40
1	0	1	Covered	T1,T2,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486254568	1082704	0	0
DepthKnown_A	487003588	486626672	0	0
RvalidKnown_A	487003588	486626672	0	0
WreadyKnown_A	487003588	486626672	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	486618248	1165278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486254568	1082704	0	0
T2	5738	3336	0	0
T3	2180	0	0	0
T4	1209862	0	0	0
T6	11068	0	0	0
T10	2824	507	0	0
T11	0	807	0	0
T19	0	1748	0	0
T20	0	10199	0	0
T21	0	3385	0	0
T22	5090	0	0	0
T23	2024	0	0	0
T24	3358	0	0	0
T25	2482	0	0	0
T31	0	47	0	0
T32	0	638	0	0
T47	0	455	0	0
T59	2310	0	0	0
T76	0	585	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487003588	486626672	0	0
T1	46098	25072	0	0
T2	5738	5636	0	0
T3	2180	2064	0	0
T4	1209862	1209840	0	0
T6	11068	10912	0	0
T10	2824	2646	0	0
T22	5090	4914	0	0
T23	2024	1852	0	0
T24	3358	3258	0	0
T25	2482	2294	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487003588	486626672	0	0
T1	46098	25072	0	0
T2	5738	5636	0	0
T3	2180	2064	0	0
T4	1209862	1209840	0	0
T6	11068	10912	0	0
T10	2824	2646	0	0
T22	5090	4914	0	0
T23	2024	1852	0	0
T24	3358	3258	0	0
T25	2482	2294	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487003588	486626672	0	0
T1	46098	25072	0	0
T2	5738	5636	0	0
T3	2180	2064	0	0
T4	1209862	1209840	0	0
T6	11068	10912	0	0
T10	2824	2646	0	0
T22	5090	4914	0	0
T23	2024	1852	0	0
T24	3358	3258	0	0
T25	2482	2294	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	486618248	1165278	0	0
T2	5738	3336	0	0
T3	2180	0	0	0
T4	1209862	0	0	0
T6	11068	0	0	0
T10	2824	507	0	0
T11	0	807	0	0
T15	0	476	0	0
T19	0	1748	0	0
T20	0	10199	0	0
T21	0	3385	0	0
T22	5090	0	0	0
T23	2024	0	0	0
T24	3358	0	0	0
T25	2482	0	0	0
T31	0	47	0	0
T32	0	638	0	0
T48	0	248	0	0
T59	2310	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T58,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T77
1	0	1	Covered	T1,T2,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	243127284	535677	0	0
DepthKnown_A	243501794	243313336	0	0
RvalidKnown_A	243501794	243313336	0	0
WreadyKnown_A	243501794	243313336	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	243309124	576646	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243127284	535677	0	0
T2	2869	1592	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	251	0	0
T11	0	395	0	0
T19	0	840	0	0
T20	0	5095	0	0
T21	0	1687	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T31	0	11	0	0
T32	0	277	0	0
T47	0	234	0	0
T59	1155	0	0	0
T76	0	297	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	243309124	576646	0	0
T2	2869	1592	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	251	0	0
T11	0	395	0	0
T15	0	243	0	0
T19	0	840	0	0
T20	0	5095	0	0
T21	0	1687	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T31	0	11	0	0
T32	0	277	0	0
T48	0	125	0	0
T59	1155	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36,T37,T75
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T40
1	0	1	Covered	T1,T2,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	243127284	547027	0	0
DepthKnown_A	243501794	243313336	0	0
RvalidKnown_A	243501794	243313336	0	0
WreadyKnown_A	243501794	243313336	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	243309124	588632	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243127284	547027	0	0
T2	2869	1744	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	256	0	0
T11	0	412	0	0
T19	0	908	0	0
T20	0	5104	0	0
T21	0	1698	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T31	0	36	0	0
T32	0	361	0	0
T47	0	221	0	0
T59	1155	0	0	0
T76	0	288	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	243309124	588632	0	0
T2	2869	1744	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	256	0	0
T11	0	412	0	0
T15	0	233	0	0
T19	0	908	0	0
T20	0	5104	0	0
T21	0	1698	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T31	0	36	0	0
T32	0	361	0	0
T48	0	123	0	0
T59	1155	0	0	0