Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	129	1			T22	1		T78	1		T40	1
auto_req_mode	146	1			T1	1		T2	1		T9	1
sw_mode	3033	1			T3	13		T4	22		T5	8

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

308

1

T1

1

T2

1

T9

1

single

92

1

T18

1

T76

1

T77

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1300	1			T9	1		T18	1		T22	1
auto[2]	215	1			T236	5		T237	1		T293	53
auto[3]	16	1			T294	1		T295	1		T296	7
auto[4]	101	1			T3	13		T4	22		T86	1
auto[5]	194	1			T39	1		T44	1		T297	8
auto[6]	323	1			T59	1		T38	98		T298	11
auto[7]	1159	1			T1	1		T2	1		T5	8

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	83	1			T22	1		T78	1		T60	1
auto[1]	auto_req_mode	82	1			T9	1		T18	1		T19	1
auto[1]	sw_mode	1135	1			T74	1		T75	1		T76	1
auto[2]	boot_req_mode	2	1			T299	1		T300	1		-	-
auto[2]	auto_req_mode	5	1			T237	1		T301	1		T302	1
auto[2]	sw_mode	208	1			T236	5		T293	53		T303	1
auto[3]	boot_req_mode	2	1			T304	1		T305	1		-	-
auto[3]	auto_req_mode	3	1			T294	1		T295	1		T306	1
auto[3]	sw_mode	11	1			T296	7		T307	1		T308	1
auto[4]	boot_req_mode	4	1			T86	1		T309	1		T310	1
auto[4]	auto_req_mode	5	1			T71	1		T311	1		T312	1
auto[4]	sw_mode	92	1			T3	13		T4	22		T313	1
auto[5]	boot_req_mode	5	1			T314	1		T315	1		T316	1
auto[5]	auto_req_mode	2	1			T317	1		T318	1		-	-
auto[5]	sw_mode	187	1			T39	1		T44	1		T297	8
auto[6]	boot_req_mode	3	1			T319	1		T320	1		T321	1
auto[6]	auto_req_mode	3	1			T235	1		T322	1		T323	1
auto[6]	sw_mode	317	1			T59	1		T38	98		T298	11
auto[7]	boot_req_mode	30	1			T40	1		T43	1		T87	1
auto[7]	auto_req_mode	46	1			T1	1		T2	1		T47	1
auto[7]	sw_mode	1083	1			T5	8		T41	1		T73	11