Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	724323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5825150

1

T1

38

T2

62

T3

308

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1730390	1			T1	32		T2	111		T3	516
values[0x0]	2227584	1			T1	17		T2	32		T3	150
values[0x1]	2591499	1			T1	22		T2	32		T3	165

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	357642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6191831

1

T1

47

T2

100

T3

440

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27108	1			T3	4		T9	2		T4	431
valid_sources[0x01]	25270	1			T2	1		T3	2		T9	1
valid_sources[0x02]	25111	1			T3	6		T4	405		T37	605
valid_sources[0x03]	27009	1			T2	1		T4	463		T18	1
valid_sources[0x04]	25409	1			T3	3		T9	2		T20	1
valid_sources[0x05]	24313	1			T3	3		T20	1		T4	251
valid_sources[0x06]	24496	1			T9	1		T4	85		T77	5
valid_sources[0x07]	26357	1			T2	1		T3	4		T4	582
valid_sources[0x08]	24576	1			T2	1		T3	4		T4	126
valid_sources[0x09]	24224	1			T3	4		T20	1		T4	724
valid_sources[0x0a]	25458	1			T3	3		T4	406		T18	1
valid_sources[0x0b]	23936	1			T3	1		T9	1		T20	1
valid_sources[0x0c]	24948	1			T2	1		T3	5		T9	1
valid_sources[0x0d]	25257	1			T2	1		T3	7		T4	103
valid_sources[0x0e]	25605	1			T3	2		T4	98		T51	1
valid_sources[0x0f]	26903	1			T2	2		T3	9		T9	1
valid_sources[0x10]	24500	1			T2	3		T20	1		T4	36
valid_sources[0x11]	26834	1			T20	3		T4	133		T37	602
valid_sources[0x12]	25834	1			T3	2		T4	570		T18	1
valid_sources[0x13]	26903	1			T2	1		T9	1		T4	441
valid_sources[0x14]	27122	1			T2	1		T3	2		T4	197
valid_sources[0x15]	24371	1			T2	2		T3	7		T4	252
valid_sources[0x16]	26133	1			T2	1		T3	3		T9	1
valid_sources[0x17]	25438	1			T2	1		T3	3		T4	531
valid_sources[0x18]	24249	1			T3	2		T9	1		T4	520
valid_sources[0x19]	24813	1			T3	2		T9	1		T4	272
valid_sources[0x1a]	25367	1			T3	4		T4	235		T18	1
valid_sources[0x1b]	26351	1			T2	1		T3	2		T4	196
valid_sources[0x1c]	24334	1			T2	2		T3	7		T4	135
valid_sources[0x1d]	25791	1			T3	7		T4	309		T27	2
valid_sources[0x1e]	25175	1			T3	2		T4	424		T18	1
valid_sources[0x1f]	26078	1			T3	2		T4	299		T18	2
valid_sources[0x20]	25470	1			T3	13		T4	24		T39	2
valid_sources[0x21]	25731	1			T3	1		T9	3		T4	571
valid_sources[0x22]	25240	1			T20	1		T4	41		T18	1
valid_sources[0x23]	27703	1			T2	1		T3	3		T4	467
valid_sources[0x24]	24488	1			T3	1		T4	343		T75	1
valid_sources[0x25]	24937	1			T3	1		T4	428		T37	564
valid_sources[0x26]	26260	1			T4	209		T6	1		T37	605
valid_sources[0x27]	25343	1			T2	2		T20	1		T4	413
valid_sources[0x28]	26104	1			T20	1		T4	352		T39	1
valid_sources[0x29]	24836	1			T2	1		T3	7		T4	398
valid_sources[0x2a]	25597	1			T2	1		T3	3		T4	286
valid_sources[0x2b]	24477	1			T3	7		T9	2		T4	75
valid_sources[0x2c]	25957	1			T20	1		T4	184		T75	1
valid_sources[0x2d]	27329	1			T3	3		T4	209		T72	1
valid_sources[0x2e]	25545	1			T3	4		T9	2		T4	584
valid_sources[0x2f]	24805	1			T2	1		T3	4		T4	810
valid_sources[0x30]	26964	1			T9	3		T20	1		T4	176
valid_sources[0x31]	25972	1			T3	4		T4	320		T75	2
valid_sources[0x32]	24361	1			T2	1		T4	248		T18	1
valid_sources[0x33]	27914	1			T3	1		T9	1		T20	3
valid_sources[0x34]	26599	1			T2	2		T3	4		T9	1
valid_sources[0x35]	26814	1			T2	1		T3	7		T4	525
valid_sources[0x36]	24602	1			T3	6		T4	355		T18	1
valid_sources[0x37]	28286	1			T3	4		T4	651		T77	1
valid_sources[0x38]	27689	1			T2	2		T3	4		T9	1
valid_sources[0x39]	26231	1			T2	1		T4	499		T37	569
valid_sources[0x3a]	25396	1			T3	2		T4	285		T72	1
valid_sources[0x3b]	24736	1			T2	2		T3	5		T9	1
valid_sources[0x3c]	24387	1			T3	3		T4	252		T27	1
valid_sources[0x3d]	27451	1			T3	2		T4	411		T75	1
valid_sources[0x3e]	24612	1			T3	2		T9	1		T4	213
valid_sources[0x3f]	24867	1			T2	1		T4	382		T18	1
valid_sources[0x40]	25552	1			T2	2		T9	1		T4	431
valid_sources[0x41]	23877	1			T3	1		T4	199		T18	2
valid_sources[0x42]	23414	1			T2	1		T3	1		T9	1
valid_sources[0x43]	25386	1			T3	8		T9	3		T4	199
valid_sources[0x44]	25696	1			T4	397		T40	2		T37	551
valid_sources[0x45]	25321	1			T4	149		T18	1		T37	528
valid_sources[0x46]	26277	1			T3	3		T4	273		T37	571
valid_sources[0x47]	26158	1			T2	1		T4	293		T72	1
valid_sources[0x48]	24944	1			T3	6		T9	2		T20	2
valid_sources[0x49]	26015	1			T2	3		T3	2		T20	1
valid_sources[0x4a]	24352	1			T2	1		T3	2		T4	179
valid_sources[0x4b]	23515	1			T3	11		T4	451		T75	1
valid_sources[0x4c]	25204	1			T4	472		T37	593		T43	48
valid_sources[0x4d]	25469	1			T3	13		T20	2		T4	311
valid_sources[0x4e]	24382	1			T2	1		T3	19		T9	1
valid_sources[0x4f]	25825	1			T2	1		T3	2		T4	45
valid_sources[0x50]	25442	1			T2	1		T3	3		T9	1
valid_sources[0x51]	26538	1			T3	5		T4	222		T18	1
valid_sources[0x52]	25332	1			T2	2		T3	10		T4	52
valid_sources[0x53]	25257	1			T3	7		T20	1		T4	229
valid_sources[0x54]	26904	1			T4	179		T37	584		T82	5
valid_sources[0x55]	26209	1			T2	2		T3	1		T9	2
valid_sources[0x56]	25020	1			T3	2		T4	488		T37	546
valid_sources[0x57]	27531	1			T4	294		T72	1		T39	1
valid_sources[0x58]	24451	1			T2	1		T9	1		T4	20
valid_sources[0x59]	25111	1			T3	5		T4	164		T77	10
valid_sources[0x5a]	25399	1			T4	103		T39	1		T37	551
valid_sources[0x5b]	25558	1			T3	3		T20	2		T4	240
valid_sources[0x5c]	24852	1			T2	1		T20	1		T4	158
valid_sources[0x5d]	24865	1			T4	362		T18	2		T51	1
valid_sources[0x5e]	23438	1			T2	2		T3	7		T20	2
valid_sources[0x5f]	24138	1			T2	1		T3	11		T4	393
valid_sources[0x60]	26277	1			T2	1		T3	10		T4	704
valid_sources[0x61]	24489	1			T3	5		T4	648		T77	2
valid_sources[0x62]	24254	1			T2	1		T9	1		T4	380
valid_sources[0x63]	25598	1			T2	1		T3	2		T9	2
valid_sources[0x64]	24785	1			T2	1		T3	4		T9	1
valid_sources[0x65]	24383	1			T2	1		T3	1		T4	90
valid_sources[0x66]	25552	1			T3	3		T4	275		T37	608
valid_sources[0x67]	26828	1			T3	4		T4	967		T18	2
valid_sources[0x68]	27559	1			T3	1		T4	820		T18	2
valid_sources[0x69]	25770	1			T2	1		T3	3		T20	1
valid_sources[0x6a]	24445	1			T3	2		T9	1		T20	1
valid_sources[0x6b]	25634	1			T2	2		T3	3		T9	1
valid_sources[0x6c]	27791	1			T3	9		T4	811		T72	1
valid_sources[0x6d]	26376	1			T2	3		T3	3		T4	461
valid_sources[0x6e]	24262	1			T2	1		T3	4		T4	349
valid_sources[0x6f]	26538	1			T3	6		T9	1		T4	357
valid_sources[0x70]	24064	1			T3	4		T9	1		T4	286
valid_sources[0x71]	26105	1			T2	1		T3	4		T9	1
valid_sources[0x72]	24948	1			T3	5		T4	295		T5	503
valid_sources[0x73]	27347	1			T2	1		T3	6		T4	804
valid_sources[0x74]	24576	1			T3	5		T4	80		T18	1
valid_sources[0x75]	25700	1			T3	13		T4	557		T18	1
valid_sources[0x76]	25490	1			T3	3		T20	1		T4	74
valid_sources[0x77]	24166	1			T3	4		T4	248		T75	1
valid_sources[0x78]	25591	1			T2	2		T3	3		T4	178
valid_sources[0x79]	24862	1			T3	1		T20	1		T4	105
valid_sources[0x7a]	27649	1			T2	2		T3	1		T4	496
valid_sources[0x7b]	25553	1			T4	208		T6	1		T37	569
valid_sources[0x7c]	26532	1			T3	1		T4	171		T77	1
valid_sources[0x7d]	25336	1			T2	2		T3	2		T4	384
valid_sources[0x7e]	28286	1			T2	4		T3	2		T4	177
valid_sources[0x7f]	25597	1			T3	1		T4	115		T6	1
valid_sources[0x80]	24835	1			T4	31		T27	2		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1466018

1

T1

5

T2

3

T3

102

values[0x0]

all_enables

biggest_size

2181676

1

T1

15

T2

30

T3

108

values[0x1]

all_enables

biggest_size

2177456

1

T1

18

T2

29

T3

98