Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2828	1			T1	2		T2	3		T3	10
non_zero_bins[1]	2059	1			T2	3		T3	6		T9	4
zero	9721	1			T1	6		T2	2		T3	30

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	570	1			T3	3		T4	2		T5	1
uni	3857	1			T1	1		T2	1		T3	14
gen	4649	1			T1	4		T2	4		T3	13
res	910	1			T1	2		T2	2		T3	2
ins	4622	1			T1	1		T2	1		T3	14

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9555

1

T1

7

T2

5

T3

36

mubi_true

5053

1

T1

1

T2

3

T3

10

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

18

1

T50

1

T83

1

T93

1

pass

14590

1

T1

8

T2

8

T3

46

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	145	1			T37	2		T38	3		T102	1
upd	non_zero_bins[0]	pass	mubi_true	127	1			T3	2		T37	5		T44	1
upd	non_zero_bins[1]	pass	mubi_false	95	1			T4	1		T76	1		T37	4
upd	non_zero_bins[1]	pass	mubi_true	95	1			T3	1		T5	1		T37	2
upd	zero	pass	mubi_false	57	1			T37	1		T38	2		T102	2
upd	zero	pass	mubi_true	51	1			T4	1		T37	3		T38	2
uni	zero	pass	mubi_false	2844	1			T1	1		T2	1		T3	13
uni	zero	pass	mubi_true	1013	1			T3	1		T4	10		T5	3
gen	non_zero_bins[0]	pass	mubi_false	486	1			T1	1		T2	3		T3	3
gen	non_zero_bins[0]	pass	mubi_true	556	1			T4	2		T75	1		T37	6
gen	non_zero_bins[1]	pass	mubi_false	413	1			T2	1		T9	4		T4	2
gen	non_zero_bins[1]	pass	mubi_true	387	1			T3	2		T77	1		T39	1
gen	zero	fail	mubi_false	16	1			T50	1		T83	1		T68	1
gen	zero	pass	mubi_false	2004	1			T1	3		T3	7		T4	15
gen	zero	pass	mubi_true	787	1			T3	1		T20	2		T4	3
res	non_zero_bins[0]	pass	mubi_false	222	1			T9	2		T4	1		T37	3
res	non_zero_bins[0]	pass	mubi_true	203	1			T18	3		T40	1		T37	7
res	non_zero_bins[1]	pass	mubi_false	128	1			T19	3		T77	2		T38	2
res	non_zero_bins[1]	pass	mubi_true	148	1			T2	2		T3	1		T37	1
res	zero	fail	mubi_false	2	1			T93	1		T149	1		-	-
res	zero	pass	mubi_false	119	1			T1	2		T3	1		T18	2
res	zero	pass	mubi_true	88	1			T4	1		T39	1		T37	1
ins	non_zero_bins[0]	pass	mubi_false	522	1			T3	3		T4	3		T5	1
ins	non_zero_bins[0]	pass	mubi_true	567	1			T1	1		T3	2		T9	1
ins	non_zero_bins[1]	pass	mubi_false	402	1			T3	2		T4	2		T5	1
ins	non_zero_bins[1]	pass	mubi_true	391	1			T18	1		T5	2		T37	8
ins	zero	pass	mubi_false	2100	1			T3	7		T20	1		T4	14
ins	zero	pass	mubi_true	640	1			T2	1		T20	1		T4	4

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded