Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.33	100.00	94.44		94.59	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	100.00	94.44		94.59	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T22,T26
1	1	Covered	T22,T27,T26

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T19,T6
1	1	Covered	T1,T2,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T27,T28
1	0	Covered	T26,T6,T13

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T20,T27,T28
1	Covered	T26,T6,T13

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T20,T27,T28
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T20,T27,T26
1	Covered	T26,T6,T13

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	70	94.59
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T2,T9
AutoCaptGenCnt	143	Covered	T1,T2,T9
AutoCaptReseedCnt	141	Covered	T1,T2,T9
AutoDispatch	125	Covered	T1,T2,T9
AutoFirstAckWait	119	Covered	T1,T2,T9
AutoLoadIns	69	Covered	T1,T2,T9
AutoSendGenCmd	150	Covered	T1,T2,T9
AutoSendReseedCmd	162	Covered	T1,T2,T9
BootDone	98	Covered	T22,T26,T78
BootGenAckWait	90	Covered	T22,T27,T26
BootInsAckWait	80	Covered	T22,T27,T26
BootLoadGen	85	Covered	T22,T27,T26
BootLoadIns	65	Covered	T22,T27,T26
BootLoadUni	102	Covered	T40,T28,T50
BootPulse	94	Covered	T22,T26,T78
BootUniAckWait	107	Covered	T40,T28,T50
Error	188	Covered	T26,T6,T13
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T20,T27,T28
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T2,T9
AutoAckWait->Error	188	Covered	T113,T114
AutoAckWait->Idle	211	Covered	T18,T19,T85
AutoAckWait->RejectCsrngEntropy	188	Covered	T50,T83,T115
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T2,T9
AutoCaptGenCnt->Error	188	Covered	T116,T117,T118
AutoCaptGenCnt->Idle	211	Covered	T18,T119,T120
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T20,T121,T122
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T2,T9
AutoCaptReseedCnt->Error	188	Covered	T6,T53,T123
AutoCaptReseedCnt->Idle	211	Covered	T19,T124,T125
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T126,T127,T128
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T2,T9
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T2,T9
AutoDispatch->Error	188	Not Covered
AutoDispatch->Idle	138	Covered	T1,T2,T9
AutoDispatch->RejectCsrngEntropy	188	Covered	T129,T130
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T2,T9
AutoFirstAckWait->Error	188	Covered	T131,T132
AutoFirstAckWait->Idle	211	Covered	T133,T134,T135
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T42,T89,T136
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T2,T9
AutoLoadIns->Error	188	Covered	T137,T138,T139
AutoLoadIns->Idle	211	Covered	T6,T7,T83
AutoLoadIns->RejectCsrngEntropy	188	Covered	T28,T94,T140
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T2,T9
AutoSendGenCmd->Error	188	Not Covered
AutoSendGenCmd->Idle	211	Covered	T85,T141,T142
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T143,T111,T144
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T2,T9
AutoSendReseedCmd->Error	188	Covered	T145
AutoSendReseedCmd->Idle	211	Covered	T146,T147,T148
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T93,T149,T69
BootDone->BootLoadUni	102	Covered	T40,T28,T50
BootDone->Error	188	Covered	T26,T52,T54
BootDone->Idle	211	Covered	T13,T88,T150
BootDone->RejectCsrngEntropy	188	Covered	T151,T152,T153
BootGenAckWait->BootPulse	94	Covered	T22,T26,T78
BootGenAckWait->Error	188	Covered	T154,T155,T156
BootGenAckWait->Idle	211	Covered	T45,T157,T158
BootGenAckWait->RejectCsrngEntropy	188	Covered	T27,T108,T159
BootInsAckWait->BootLoadGen	85	Covered	T22,T27,T26
BootInsAckWait->Error	188	Covered	T13,T55,T158
BootInsAckWait->Idle	211	Covered	T26,T14,T79
BootInsAckWait->RejectCsrngEntropy	188	Covered	T105,T92,T160
BootLoadGen->BootGenAckWait	90	Covered	T22,T27,T26
BootLoadGen->Error	188	Covered	T161,T162,T163
BootLoadGen->Idle	211	Covered	T78,T60,T164
BootLoadGen->RejectCsrngEntropy	188	Covered	T165,T166
BootLoadIns->BootInsAckWait	80	Covered	T22,T27,T26
BootLoadIns->Error	188	Covered	T79,T167,T168
BootLoadIns->Idle	211	Covered	T169,T170,T171
BootLoadIns->RejectCsrngEntropy	188	Covered	T107,T172,T173
BootLoadUni->BootUniAckWait	107	Covered	T40,T28,T50
BootLoadUni->Error	188	Not Covered
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T174,T175,T176
BootPulse->BootDone	98	Covered	T22,T26,T78
BootPulse->Error	188	Covered	T14,T177,T178
BootPulse->Idle	211	Covered	T22,T179,T180
BootPulse->RejectCsrngEntropy	188	Covered	T104,T181,T182
BootUniAckWait->Error	188	Covered	T80,T183
BootUniAckWait->Idle	112	Covered	T40,T28,T50
BootUniAckWait->RejectCsrngEntropy	188	Covered	T106,T112,T184
Idle->AutoLoadIns	69	Covered	T1,T2,T9
Idle->BootLoadIns	65	Covered	T22,T27,T26
Idle->Error	188	Covered	T15,T16,T17
Idle->RejectCsrngEntropy	188	Covered	T28,T42,T92
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T185,T186
RejectCsrngEntropy->Idle	211	Covered	T20,T27,T28
SWPortMode->Error	188	Covered	T187,T188,T189
SWPortMode->Idle	211	Covered	T3,T20,T4
SWPortMode->RejectCsrngEntropy	188	Covered	T20,T27,T50

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T26
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T26
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T26
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T26
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T26
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T26
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T26
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T26,T78
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T40,T28,T50
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T22,T26,T78
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T28,T50
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T40,T28,T108
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T40,T28,T50
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T9
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T9
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T9
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T9
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T27,T28
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T81,T8

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T26,T6,T13
1	0	1	-	Not Covered
1	0	0	-	Covered	T20,T27,T28
0	-	-	1	Covered	T20,T18,T22
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	224193479	135906	0	0
FpvSecCmErrorStEscalate_A	224193479	136942	0	0
u_state_regs_A	224158655	223976642	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	135906	0	0
T6	1265	410	0	0
T7	0	1020	0	0
T8	0	413	0	0
T13	801	374	0	0
T14	0	352	0	0
T26	1846	1070	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1129	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	300	0	0
T80	0	387	0	0
T81	0	440	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	136942	0	0
T6	1265	411	0	0
T7	0	1021	0	0
T8	0	414	0	0
T13	801	375	0	0
T14	0	353	0	0
T26	1846	1071	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1130	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	301	0	0
T80	0	388	0	0
T81	0	441	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224158655	223976642	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0