Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T26,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T180,T190
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T18,T60,T45
DataWait->Error	99	Covered	T13,T52,T8
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T3,T5,T72
EndPointClear->Error	99	Covered	T79,T191,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T3,T20,T4
Idle->Error	99	Covered	T26,T6,T13

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	Covered	T26,T79,T80

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T6,T13
0	1	Covered	T20,T18,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1569354353	964042	0	0
FpvSecCmErrorStEscalate_A	1569354353	971294	0	0
u_state_regs_A	1569319529	1568045438	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1569354353	964042	0	0
T6	8855	2870	0	0
T7	0	7490	0	0
T8	0	3241	0	0
T13	5607	2618	0	0
T14	0	2464	0	0
T26	12922	7440	0	0
T28	16436	0	0	0
T37	2804298	0	0	0
T40	9464	0	0	0
T52	0	7903	0	0
T58	12012	0	0	0
T59	32186	0	0	0
T60	6223	0	0	0
T78	7315	0	0	0
T79	0	2050	0	0
T80	0	2659	0	0
T81	0	3430	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1569354353	971294	0	0
T6	8855	2877	0	0
T7	0	7497	0	0
T8	0	3248	0	0
T13	5607	2625	0	0
T14	0	2471	0	0
T26	12922	7447	0	0
T28	16436	0	0	0
T37	2804298	0	0	0
T40	9464	0	0	0
T52	0	7910	0	0
T58	12012	0	0	0
T59	32186	0	0	0
T60	6223	0	0	0
T78	7315	0	0	0
T79	0	2057	0	0
T80	0	2666	0	0
T81	0	3437	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1569319529	1568045438	0	0
T1	20965	20419	0	0
T2	14910	14392	0	0
T3	159684	152439	0	0
T4	1670235	1670158	0	0
T5	89705	86590	0	0
T9	29911	29267	0	0
T18	11816	11347	0	0
T20	15519	14931	0	0
T21	9996	9513	0	0
T22	6951	6524	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T9,T20
DataWait	75	Covered	T3,T9,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T26,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T9,T20
DataWait->AckPls	80	Covered	T3,T9,T20
DataWait->Disabled	107	Covered	T119,T192,T193
DataWait->Error	99	Covered	T13,T52,T8
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T3,T5,T72
EndPointClear->Error	99	Covered	T191,T15,T194
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T9,T20
Idle->Disabled	107	Covered	T3,T20,T4
Idle->Error	99	Covered	T6,T14,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T9,T20
Idle	-	1	0	-	Covered	T3,T9,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T9,T20
DataWait	-	-	-	0	Covered	T3,T9,T20
AckPls	-	-	-	-	Covered	T3,T9,T20
Error	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	Covered	T26,T79,T80

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T6,T13
0	1	Covered	T20,T18,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	224193479	135706	0	0
FpvSecCmErrorStEscalate_A	224193479	136742	0	0
u_state_regs_A	224158655	223976642	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	135706	0	0
T6	1265	410	0	0
T7	0	1070	0	0
T8	0	463	0	0
T13	801	374	0	0
T14	0	352	0	0
T26	1846	1020	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1129	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	250	0	0
T80	0	337	0	0
T81	0	490	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	136742	0	0
T6	1265	411	0	0
T7	0	1071	0	0
T8	0	464	0	0
T13	801	375	0	0
T14	0	353	0	0
T26	1846	1021	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1130	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	251	0	0
T80	0	338	0	0
T81	0	491	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224158655	223976642	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T18,T39
DataWait	75	Covered	T2,T18,T39
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T26,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T18,T39
DataWait->AckPls	80	Covered	T2,T18,T39
DataWait->Disabled	107	Covered	T195,T196,T197
DataWait->Error	99	Covered	T185,T131,T198
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T3,T5,T72
EndPointClear->Error	99	Covered	T79,T191,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T18,T39
Idle->Disabled	107	Covered	T3,T20,T4
Idle->Error	99	Covered	T26,T6,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T18,T39
Idle	-	1	0	-	Covered	T2,T18,T39
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T18,T39
DataWait	-	-	-	0	Covered	T2,T18,T39
AckPls	-	-	-	-	Covered	T2,T18,T39
Error	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T6,T13
0	1	Covered	T20,T18,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	224193479	138056	0	0
FpvSecCmErrorStEscalate_A	224193479	139092	0	0
u_state_regs_A	224193479	224011466	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	138056	0	0
T6	1265	410	0	0
T7	0	1070	0	0
T8	0	463	0	0
T13	801	374	0	0
T14	0	352	0	0
T26	1846	1070	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1129	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	300	0	0
T80	0	387	0	0
T81	0	490	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	139092	0	0
T6	1265	411	0	0
T7	0	1071	0	0
T8	0	464	0	0
T13	801	375	0	0
T14	0	353	0	0
T26	1846	1071	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1130	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	301	0	0
T80	0	388	0	0
T81	0	491	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T40
DataWait	75	Covered	T1,T2,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T26,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T40
DataWait->AckPls	80	Covered	T1,T2,T40
DataWait->Disabled	107	Covered	T60,T157,T199
DataWait->Error	99	Covered	T54,T200,T183
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T3,T5,T72
EndPointClear->Error	99	Covered	T79,T191,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T40
Idle->Disabled	107	Covered	T3,T20,T4
Idle->Error	99	Covered	T26,T6,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T40
Idle	-	1	0	-	Covered	T1,T2,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T40
DataWait	-	-	-	0	Covered	T1,T2,T40
AckPls	-	-	-	-	Covered	T1,T2,T40
Error	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T6,T13
0	1	Covered	T20,T18,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	224193479	138056	0	0
FpvSecCmErrorStEscalate_A	224193479	139092	0	0
u_state_regs_A	224193479	224011466	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	138056	0	0
T6	1265	410	0	0
T7	0	1070	0	0
T8	0	463	0	0
T13	801	374	0	0
T14	0	352	0	0
T26	1846	1070	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1129	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	300	0	0
T80	0	387	0	0
T81	0	490	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	139092	0	0
T6	1265	411	0	0
T7	0	1071	0	0
T8	0	464	0	0
T13	801	375	0	0
T14	0	353	0	0
T26	1846	1071	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1130	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	301	0	0
T80	0	388	0	0
T81	0	491	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T39,T40,T41
DataWait	75	Covered	T39,T40,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T26,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T39,T40,T41
DataWait->AckPls	80	Covered	T39,T40,T41
DataWait->Disabled	107	Covered	T45,T85,T164
DataWait->Error	99	Covered	T7,T201,T202
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T3,T5,T72
EndPointClear->Error	99	Covered	T79,T191,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T39,T40,T41
Idle->Disabled	107	Covered	T3,T20,T4
Idle->Error	99	Covered	T26,T6,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T39,T40,T41
Idle	-	1	0	-	Covered	T39,T40,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T39,T40,T41
DataWait	-	-	-	0	Covered	T39,T40,T41
AckPls	-	-	-	-	Covered	T39,T40,T41
Error	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T6,T13
0	1	Covered	T20,T18,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	224193479	138056	0	0
FpvSecCmErrorStEscalate_A	224193479	139092	0	0
u_state_regs_A	224193479	224011466	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	138056	0	0
T6	1265	410	0	0
T7	0	1070	0	0
T8	0	463	0	0
T13	801	374	0	0
T14	0	352	0	0
T26	1846	1070	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1129	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	300	0	0
T80	0	387	0	0
T81	0	490	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	139092	0	0
T6	1265	411	0	0
T7	0	1071	0	0
T8	0	464	0	0
T13	801	375	0	0
T14	0	353	0	0
T26	1846	1071	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1130	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	301	0	0
T80	0	388	0	0
T81	0	491	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T40,T42,T41
DataWait	75	Covered	T40,T42,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T26,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T40,T42,T41
DataWait->AckPls	80	Covered	T40,T42,T41
DataWait->Disabled	107	Covered	T203,T204,T205
DataWait->Error	99	Covered	T178,T206
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T3,T5,T72
EndPointClear->Error	99	Covered	T79,T191,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T40,T42,T41
Idle->Disabled	107	Covered	T3,T20,T4
Idle->Error	99	Covered	T26,T6,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T40,T42,T41
Idle	-	1	0	-	Covered	T40,T42,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T40,T42,T41
DataWait	-	-	-	0	Covered	T40,T42,T41
AckPls	-	-	-	-	Covered	T40,T42,T41
Error	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T6,T13
0	1	Covered	T20,T18,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	224193479	138056	0	0
FpvSecCmErrorStEscalate_A	224193479	139092	0	0
u_state_regs_A	224193479	224011466	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	138056	0	0
T6	1265	410	0	0
T7	0	1070	0	0
T8	0	463	0	0
T13	801	374	0	0
T14	0	352	0	0
T26	1846	1070	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1129	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	300	0	0
T80	0	387	0	0
T81	0	490	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	139092	0	0
T6	1265	411	0	0
T7	0	1071	0	0
T8	0	464	0	0
T13	801	375	0	0
T14	0	353	0	0
T26	1846	1071	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1130	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	301	0	0
T80	0	388	0	0
T81	0	491	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T40,T28
DataWait	75	Covered	T19,T40,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T26,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T40,T28
DataWait->AckPls	80	Covered	T19,T40,T28
DataWait->Disabled	107	Covered	T207,T142,T120
DataWait->Error	99	Covered	T80,T208,T209
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T3,T5,T72
EndPointClear->Error	99	Covered	T79,T191,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T19,T40,T28
Idle->Disabled	107	Covered	T3,T20,T4
Idle->Error	99	Covered	T26,T6,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T19,T40,T28
Idle	-	1	0	-	Covered	T19,T40,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T19,T40,T28
DataWait	-	-	-	0	Covered	T19,T40,T28
AckPls	-	-	-	-	Covered	T19,T40,T28
Error	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T6,T13
0	1	Covered	T20,T18,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	224193479	138056	0	0
FpvSecCmErrorStEscalate_A	224193479	139092	0	0
u_state_regs_A	224193479	224011466	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	138056	0	0
T6	1265	410	0	0
T7	0	1070	0	0
T8	0	463	0	0
T13	801	374	0	0
T14	0	352	0	0
T26	1846	1070	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1129	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	300	0	0
T80	0	387	0	0
T81	0	490	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	139092	0	0
T6	1265	411	0	0
T7	0	1071	0	0
T8	0	464	0	0
T13	801	375	0	0
T14	0	353	0	0
T26	1846	1071	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1130	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	301	0	0
T80	0	388	0	0
T81	0	491	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T18,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T18,T39,T6
DataWait	75	Covered	T18,T39,T6
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T26,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T180,T190
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T18,T39,T6
DataWait->AckPls	80	Covered	T18,T39,T6
DataWait->Disabled	107	Covered	T18,T210,T211
DataWait->Error	99	Covered	T14
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T3,T5,T72
EndPointClear->Error	99	Covered	T79,T191,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T18,T39,T6
Idle->Disabled	107	Covered	T3,T20,T4
Idle->Error	99	Covered	T26,T6,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T18,T39,T6
Idle	-	1	0	-	Covered	T18,T39,T6
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T18,T39,T6
DataWait	-	-	-	0	Covered	T18,T39,T6
AckPls	-	-	-	-	Covered	T18,T39,T6
Error	-	-	-	-	Covered	T26,T6,T13
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T6,T13
0	1	Covered	T20,T18,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	224193479	138056	0	0
FpvSecCmErrorStEscalate_A	224193479	139092	0	0
u_state_regs_A	224193479	224011466	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	138056	0	0
T6	1265	410	0	0
T7	0	1070	0	0
T8	0	463	0	0
T13	801	374	0	0
T14	0	352	0	0
T26	1846	1070	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1129	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	300	0	0
T80	0	387	0	0
T81	0	490	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	139092	0	0
T6	1265	411	0	0
T7	0	1071	0	0
T8	0	464	0	0
T13	801	375	0	0
T14	0	353	0	0
T26	1846	1071	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T52	0	1130	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	301	0	0
T80	0	388	0	0
T81	0	491	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0