Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T35,T96
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T30,T36
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	447608906	1040033	0	0
DepthKnown_A	448386958	448022932	0	0
RvalidKnown_A	448386958	448022932	0	0
WreadyKnown_A	448386958	448022932	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	447952176	1115649	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447608906	1040033	0	0
T1	5990	1525	0	0
T2	4260	647	0	0
T3	45624	0	0	0
T4	477210	0	0	0
T5	25630	0	0	0
T6	0	270	0	0
T9	8546	2926	0	0
T18	3376	2261	0	0
T19	0	3359	0	0
T20	4434	537	0	0
T21	2856	0	0	0
T22	1986	0	0	0
T28	0	351	0	0
T50	0	561	0	0
T77	0	1091	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448386958	448022932	0	0
T1	5990	5834	0	0
T2	4260	4112	0	0
T3	45624	43554	0	0
T4	477210	477188	0	0
T5	25630	24740	0	0
T9	8546	8362	0	0
T18	3376	3242	0	0
T20	4434	4266	0	0
T21	2856	2718	0	0
T22	1986	1864	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448386958	448022932	0	0
T1	5990	5834	0	0
T2	4260	4112	0	0
T3	45624	43554	0	0
T4	477210	477188	0	0
T5	25630	24740	0	0
T9	8546	8362	0	0
T18	3376	3242	0	0
T20	4434	4266	0	0
T21	2856	2718	0	0
T22	1986	1864	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448386958	448022932	0	0
T1	5990	5834	0	0
T2	4260	4112	0	0
T3	45624	43554	0	0
T4	477210	477188	0	0
T5	25630	24740	0	0
T9	8546	8362	0	0
T18	3376	3242	0	0
T20	4434	4266	0	0
T21	2856	2718	0	0
T22	1986	1864	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	447952176	1115649	0	0
T1	5990	1525	0	0
T2	4260	647	0	0
T3	45624	0	0	0
T4	477210	0	0	0
T5	25630	0	0	0
T6	0	1215	0	0
T9	8546	2926	0	0
T13	0	285	0	0
T18	3376	2261	0	0
T19	0	3359	0	0
T20	4434	537	0	0
T21	2856	0	0	0
T22	1986	0	0	0
T26	0	370	0	0
T77	0	1091	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T7,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T97
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T98
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	223804453	513366	0	0
DepthKnown_A	224193479	224011466	0	0
RvalidKnown_A	224193479	224011466	0	0
WreadyKnown_A	224193479	224011466	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	223976088	551151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223804453	513366	0	0
T1	2995	694	0	0
T2	2130	322	0	0
T3	22812	0	0	0
T4	238605	0	0	0
T5	12815	0	0	0
T6	0	81	0	0
T9	4273	1430	0	0
T18	1688	1108	0	0
T19	0	1635	0	0
T20	2217	271	0	0
T21	1428	0	0	0
T22	993	0	0	0
T28	0	179	0	0
T50	0	287	0	0
T77	0	546	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	223976088	551151	0	0
T1	2995	694	0	0
T2	2130	322	0	0
T3	22812	0	0	0
T4	238605	0	0	0
T5	12815	0	0	0
T6	0	514	0	0
T9	4273	1430	0	0
T13	0	144	0	0
T18	1688	1108	0	0
T19	0	1635	0	0
T20	2217	271	0	0
T21	1428	0	0	0
T22	993	0	0	0
T26	0	186	0	0
T77	0	546	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T35,T96
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T36,T99
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	223804453	526667	0	0
DepthKnown_A	224193479	224011466	0	0
RvalidKnown_A	224193479	224011466	0	0
WreadyKnown_A	224193479	224011466	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	223976088	564498	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223804453	526667	0	0
T1	2995	831	0	0
T2	2130	325	0	0
T3	22812	0	0	0
T4	238605	0	0	0
T5	12815	0	0	0
T6	0	189	0	0
T9	4273	1496	0	0
T18	1688	1153	0	0
T19	0	1724	0	0
T20	2217	266	0	0
T21	1428	0	0	0
T22	993	0	0	0
T28	0	172	0	0
T50	0	274	0	0
T77	0	545	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	223976088	564498	0	0
T1	2995	831	0	0
T2	2130	325	0	0
T3	22812	0	0	0
T4	238605	0	0	0
T5	12815	0	0	0
T6	0	701	0	0
T9	4273	1496	0	0
T13	0	141	0	0
T18	1688	1153	0	0
T19	0	1724	0	0
T20	2217	266	0	0
T21	1428	0	0	0
T22	993	0	0	0
T26	0	184	0	0
T77	0	545	0	0