Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	651091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5299447

1

T1

25

T2

12

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1574986	1			T1	51		T2	4		T3	26
values[0x0]	2025155	1			T1	12		T2	6		T3	13
values[0x1]	2350397	1			T1	16		T2	7		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	323801	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5626737

1

T1

40

T2

14

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23311	1			T5	5		T10	1		T38	1
valid_sources[0x01]	22285	1			T5	2		T31	1		T38	1
valid_sources[0x02]	23329	1			T3	2		T10	2		T77	1
valid_sources[0x03]	23450	1			T5	1		T10	1		T22	2
valid_sources[0x04]	23057	1			T5	1		T10	2		T34	368
valid_sources[0x05]	24144	1			T10	2		T77	1		T47	3
valid_sources[0x06]	23349	1			T5	9		T10	2		T22	1
valid_sources[0x07]	21089	1			T5	1		T10	7		T31	1
valid_sources[0x08]	22492	1			T5	2		T77	1		T47	4
valid_sources[0x09]	22946	1			T5	9		T10	5		T22	2
valid_sources[0x0a]	24465	1			T5	5		T38	1		T78	2
valid_sources[0x0b]	22296	1			T5	5		T10	4		T56	5
valid_sources[0x0c]	23259	1			T5	2		T22	1		T34	408
valid_sources[0x0d]	22105	1			T3	1		T10	1		T38	1
valid_sources[0x0e]	23843	1			T5	2		T30	4		T47	6
valid_sources[0x0f]	23700	1			T5	9		T10	1		T47	1
valid_sources[0x10]	22107	1			T5	2		T10	1		T47	2
valid_sources[0x11]	24685	1			T5	2		T38	1		T78	5
valid_sources[0x12]	24092	1			T5	1		T10	4		T22	1
valid_sources[0x13]	23563	1			T5	3		T38	2		T34	376
valid_sources[0x14]	21286	1			T5	5		T10	1		T47	2
valid_sources[0x15]	22692	1			T5	1		T10	2		T76	1
valid_sources[0x16]	23475	1			T5	2		T10	2		T22	1
valid_sources[0x17]	22342	1			T34	357		T60	3		T35	191
valid_sources[0x18]	23069	1			T5	1		T77	1		T34	383
valid_sources[0x19]	22247	1			T47	1		T34	320		T35	197
valid_sources[0x1a]	24890	1			T5	4		T38	1		T47	2
valid_sources[0x1b]	22003	1			T5	6		T38	1		T34	356
valid_sources[0x1c]	24790	1			T10	5		T22	1		T78	1
valid_sources[0x1d]	23383	1			T3	2		T5	7		T16	1
valid_sources[0x1e]	23461	1			T10	4		T38	1		T47	2
valid_sources[0x1f]	22631	1			T34	327		T35	243		T111	6
valid_sources[0x20]	23455	1			T5	1		T16	1		T47	5
valid_sources[0x21]	23291	1			T5	4		T22	2		T34	335
valid_sources[0x22]	24754	1			T24	6		T10	2		T22	2
valid_sources[0x23]	23522	1			T5	4		T34	337		T35	173
valid_sources[0x24]	22044	1			T5	1		T47	1		T78	2
valid_sources[0x25]	25420	1			T5	1		T22	2		T14	1
valid_sources[0x26]	23781	1			T31	1		T38	2		T77	1
valid_sources[0x27]	22856	1			T5	8		T31	1		T34	328
valid_sources[0x28]	23063	1			T5	2		T34	337		T35	175
valid_sources[0x29]	23173	1			T2	8		T5	1		T34	358
valid_sources[0x2a]	22209	1			T5	6		T22	1		T47	1
valid_sources[0x2b]	22379	1			T10	2		T76	1		T34	367
valid_sources[0x2c]	23578	1			T10	2		T47	2		T34	352
valid_sources[0x2d]	22532	1			T5	2		T16	1		T47	1
valid_sources[0x2e]	24454	1			T22	1		T34	340		T35	223
valid_sources[0x2f]	24282	1			T1	1		T5	7		T47	2
valid_sources[0x30]	20555	1			T1	4		T5	2		T34	386
valid_sources[0x31]	23584	1			T5	2		T10	2		T47	2
valid_sources[0x32]	22370	1			T5	10		T10	4		T22	1
valid_sources[0x33]	23244	1			T42	7		T34	367		T60	1
valid_sources[0x34]	22522	1			T1	2		T5	13		T10	1
valid_sources[0x35]	22474	1			T5	4		T34	330		T35	198
valid_sources[0x36]	23917	1			T5	1		T16	1		T22	1
valid_sources[0x37]	23005	1			T3	1		T10	2		T57	2
valid_sources[0x38]	25220	1			T1	1		T5	2		T22	1
valid_sources[0x39]	22113	1			T5	6		T34	343		T35	166
valid_sources[0x3a]	22930	1			T38	1		T47	2		T34	351
valid_sources[0x3b]	24141	1			T5	3		T22	1		T47	2
valid_sources[0x3c]	23697	1			T5	1		T22	1		T34	362
valid_sources[0x3d]	22584	1			T1	7		T5	3		T34	357
valid_sources[0x3e]	23829	1			T5	1		T10	3		T38	1
valid_sources[0x3f]	22250	1			T5	1		T10	5		T38	3
valid_sources[0x40]	25007	1			T3	1		T76	1		T47	1
valid_sources[0x41]	24848	1			T5	2		T10	1		T22	1
valid_sources[0x42]	23856	1			T3	1		T10	1		T47	1
valid_sources[0x43]	23458	1			T5	6		T10	2		T31	1
valid_sources[0x44]	22568	1			T5	8		T12	98		T38	1
valid_sources[0x45]	22953	1			T3	1		T5	3		T47	1
valid_sources[0x46]	23011	1			T5	7		T10	1		T22	33
valid_sources[0x47]	23822	1			T34	391		T35	169		T73	2
valid_sources[0x48]	24719	1			T1	5		T5	3		T10	1
valid_sources[0x49]	22849	1			T3	4		T38	1		T76	2
valid_sources[0x4a]	22278	1			T1	6		T22	1		T47	4
valid_sources[0x4b]	23643	1			T5	10		T10	3		T79	1
valid_sources[0x4c]	24833	1			T5	2		T34	347		T35	200
valid_sources[0x4d]	23350	1			T10	3		T47	6		T59	6
valid_sources[0x4e]	24147	1			T38	1		T47	1		T57	1
valid_sources[0x4f]	23256	1			T5	4		T10	3		T22	1
valid_sources[0x50]	24153	1			T5	2		T31	1		T38	2
valid_sources[0x51]	22363	1			T5	6		T16	1		T34	363
valid_sources[0x52]	24699	1			T5	16		T47	1		T57	1
valid_sources[0x53]	23629	1			T5	1		T38	2		T77	1
valid_sources[0x54]	22811	1			T5	4		T10	1		T76	1
valid_sources[0x55]	23672	1			T5	6		T10	2		T38	1
valid_sources[0x56]	23207	1			T23	9		T10	1		T47	1
valid_sources[0x57]	24769	1			T5	1		T10	7		T22	2
valid_sources[0x58]	22935	1			T5	1		T10	1		T31	1
valid_sources[0x59]	22129	1			T5	8		T81	1		T14	1
valid_sources[0x5a]	23786	1			T5	5		T10	4		T47	4
valid_sources[0x5b]	23227	1			T1	1		T3	8		T5	11
valid_sources[0x5c]	24026	1			T47	1		T78	1		T34	392
valid_sources[0x5d]	22649	1			T1	1		T5	2		T10	1
valid_sources[0x5e]	22503	1			T5	1		T47	2		T34	370
valid_sources[0x5f]	22558	1			T1	8		T2	2		T47	5
valid_sources[0x60]	24101	1			T5	2		T38	2		T47	4
valid_sources[0x61]	23022	1			T5	4		T10	1		T34	350
valid_sources[0x62]	22922	1			T5	3		T16	1		T30	1
valid_sources[0x63]	22286	1			T5	2		T34	374		T60	1
valid_sources[0x64]	23872	1			T22	2		T38	1		T47	2
valid_sources[0x65]	22878	1			T5	3		T10	6		T38	1
valid_sources[0x66]	24042	1			T1	1		T3	1		T5	7
valid_sources[0x67]	23778	1			T76	1		T14	1		T34	392
valid_sources[0x68]	25845	1			T5	3		T16	1		T22	1
valid_sources[0x69]	23112	1			T5	10		T10	1		T77	1
valid_sources[0x6a]	23793	1			T1	1		T5	2		T30	1
valid_sources[0x6b]	22417	1			T47	2		T78	1		T34	344
valid_sources[0x6c]	23168	1			T5	1		T10	2		T38	1
valid_sources[0x6d]	21432	1			T10	11		T34	336		T35	211
valid_sources[0x6e]	23014	1			T5	3		T47	2		T34	343
valid_sources[0x6f]	21451	1			T5	12		T10	6		T38	1
valid_sources[0x70]	25010	1			T1	3		T5	2		T10	6
valid_sources[0x71]	23600	1			T5	1		T10	3		T34	372
valid_sources[0x72]	23554	1			T5	5		T34	369		T35	173
valid_sources[0x73]	22368	1			T38	2		T34	415		T35	192
valid_sources[0x74]	22021	1			T10	1		T79	2		T34	376
valid_sources[0x75]	22735	1			T34	370		T35	240		T73	3
valid_sources[0x76]	24145	1			T5	4		T16	2		T42	6
valid_sources[0x77]	22805	1			T5	6		T16	1		T22	1
valid_sources[0x78]	22134	1			T1	2		T10	1		T38	1
valid_sources[0x79]	22416	1			T5	4		T10	8		T38	1
valid_sources[0x7a]	23036	1			T1	1		T2	1		T5	4
valid_sources[0x7b]	23481	1			T24	16		T5	4		T22	1
valid_sources[0x7c]	22244	1			T3	2		T16	1		T10	11
valid_sources[0x7d]	23549	1			T5	7		T42	5		T34	339
valid_sources[0x7e]	21859	1			T10	5		T77	1		T47	1
valid_sources[0x7f]	26073	1			T1	1		T5	1		T57	1
valid_sources[0x80]	22917	1			T5	3		T16	1		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1335444

1

T1

12

T2

3

T3

8

values[0x0]

all_enables

biggest_size

1982689

1

T1

9

T2

4

T3

6

values[0x1]

all_enables

biggest_size

1981314

1

T1

4

T2

5

T3

4