Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 62.50 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 24 28 53.85


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 24 28 53.85 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 2897 1 T9 2 T5 12 T10 1
non_zero_bins[1] 1953 1 T9 2 T5 5 T10 6
zero 9504 1 T1 6 T2 3 T3 5



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 555 1 T5 4 T72 2 T55 1
uni 3794 1 T9 1 T24 1 T5 16
gen 4502 1 T1 3 T2 1 T3 3
res 946 1 T1 1 T9 2 T5 1
ins 4557 1 T1 2 T2 2 T3 2



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 9510 1 T1 3 T2 1 T3 2
mubi_true 4844 1 T1 3 T2 2 T3 3



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 16 1 T23 1 T22 1 T251 1
pass 14338 1 T1 6 T2 3 T3 5



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 24 28 53.85 24
Automatically Generated Cross Bins 52 24 28 53.85 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[uni] [zero] [fail] * -- -- 2
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] * [fail] * -- -- 6


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 146 1 T5 1 T72 1 T55 1
upd non_zero_bins[0] pass mubi_true 122 1 T5 2 T34 2 T111 1
upd non_zero_bins[1] pass mubi_false 85 1 T72 1 T34 1 T35 2
upd non_zero_bins[1] pass mubi_true 84 1 T5 1 T35 1 T36 1
upd zero pass mubi_false 62 1 T35 3 T112 1 T108 1
upd zero pass mubi_true 56 1 T35 1 T111 1 T109 1
uni zero pass mubi_false 2823 1 T9 1 T24 1 T5 10
uni zero pass mubi_true 971 1 T5 6 T75 1 T76 1
gen non_zero_bins[0] pass mubi_false 562 1 T5 1 T11 5 T75 1
gen non_zero_bins[0] pass mubi_true 518 1 T5 1 T37 1 T38 1
gen non_zero_bins[1] pass mubi_false 371 1 T10 3 T11 1 T55 1
gen non_zero_bins[1] pass mubi_true 357 1 T9 1 T5 3 T10 1
gen zero fail mubi_false 13 1 T23 1 T22 1 T251 1
gen zero pass mubi_false 1946 1 T1 1 T3 1 T23 1
gen zero pass mubi_true 735 1 T1 2 T2 1 T3 2
res non_zero_bins[0] pass mubi_false 214 1 T9 2 T37 1 T34 2
res non_zero_bins[0] pass mubi_true 226 1 T11 2 T47 1 T72 1
res non_zero_bins[1] pass mubi_false 150 1 T5 1 T10 2 T38 1
res non_zero_bins[1] pass mubi_true 143 1 T47 1 T34 3 T73 1
res zero fail mubi_false 3 1 T166 1 T294 1 T295 1
res zero pass mubi_false 121 1 T1 1 T43 4 T12 2
res zero pass mubi_true 89 1 T34 1 T85 2 T296 1
ins non_zero_bins[0] pass mubi_false 524 1 T5 3 T11 1 T12 1
ins non_zero_bins[0] pass mubi_true 585 1 T5 4 T10 1 T43 1
ins non_zero_bins[1] pass mubi_false 409 1 T34 5 T35 4 T74 2
ins non_zero_bins[1] pass mubi_true 354 1 T9 1 T75 1 T47 2
ins zero pass mubi_false 2081 1 T1 1 T2 1 T3 1
ins zero pass mubi_true 604 1 T1 1 T2 1 T3 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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