Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T30
1	1	Covered	T2,T3,T23

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T43,T21,T6
1	1	Covered	T1,T9,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T23
1	0	Covered	T2,T30,T31

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T3,T23
1	Covered	T2,T30,T31

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T23
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T30,T31

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T9,T10
AutoCaptGenCnt	143	Covered	T1,T9,T10
AutoCaptReseedCnt	141	Covered	T1,T9,T10
AutoDispatch	125	Covered	T1,T9,T10
AutoFirstAckWait	119	Covered	T1,T9,T10
AutoLoadIns	69	Covered	T1,T9,T10
AutoSendGenCmd	150	Covered	T1,T9,T10
AutoSendReseedCmd	162	Covered	T1,T9,T10
BootDone	98	Covered	T2,T3,T23
BootGenAckWait	90	Covered	T2,T3,T23
BootInsAckWait	80	Covered	T2,T3,T23
BootLoadGen	85	Covered	T2,T3,T23
BootLoadIns	65	Covered	T2,T3,T23
BootLoadUni	102	Covered	T3,T23,T56
BootPulse	94	Covered	T2,T3,T23
BootUniAckWait	107	Covered	T3,T23,T56
Error	188	Covered	T2,T30,T31
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T3,T23
SWPortMode	74	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T9,T10
AutoAckWait->Error	188	Covered	T6,T8,T126
AutoAckWait->Idle	211	Covered	T43,T21,T96
AutoAckWait->RejectCsrngEntropy	188	Covered	T1,T22,T60
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T9,T10
AutoCaptGenCnt->Error	188	Covered	T127,T128
AutoCaptGenCnt->Idle	211	Covered	T129,T130,T131
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T56,T116,T132
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T9,T10
AutoCaptReseedCnt->Error	188	Covered	T7,T133,T134
AutoCaptReseedCnt->Idle	211	Covered	T21,T135,T136
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T137,T138,T139
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T9,T10
AutoDispatch->Error	188	Covered	T140
AutoDispatch->Idle	138	Covered	T9,T10,T11
AutoDispatch->RejectCsrngEntropy	188	Covered	T141,T142,T143
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T9,T10
AutoFirstAckWait->Error	188	Covered	T144,T145,T146
AutoFirstAckWait->Idle	211	Covered	T43,T147,T148
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T149,T150,T151
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T9,T10
AutoLoadIns->Error	188	Covered	T51,T52,T152
AutoLoadIns->Idle	211	Covered	T22,T60,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T113,T110,T153
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T9,T10
AutoSendGenCmd->Error	188	Covered	T154
AutoSendGenCmd->Idle	211	Covered	T155,T156,T157
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T115,T158,T159
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T9,T10
AutoSendReseedCmd->Error	188	Covered	T160,T161,T162
AutoSendReseedCmd->Idle	211	Covered	T163,T164,T165
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T120,T166,T121
BootDone->BootLoadUni	102	Covered	T3,T23,T56
BootDone->Error	188	Covered	T15,T167
BootDone->Idle	211	Covered	T168,T169,T170
BootDone->RejectCsrngEntropy	188	Covered	T171,T172,T173
BootGenAckWait->BootPulse	94	Covered	T2,T3,T23
BootGenAckWait->Error	188	Covered	T174,T175,T176
BootGenAckWait->Idle	211	Covered	T31,T91,T106
BootGenAckWait->RejectCsrngEntropy	188	Covered	T23,T177,T178
BootInsAckWait->BootLoadGen	85	Covered	T2,T3,T23
BootInsAckWait->Error	188	Covered	T179,T54,T180
BootInsAckWait->Idle	211	Covered	T2,T30,T80
BootInsAckWait->RejectCsrngEntropy	188	Covered	T46,T114,T70
BootLoadGen->BootGenAckWait	90	Covered	T2,T3,T23
BootLoadGen->Error	188	Covered	T80,T106,T181
BootLoadGen->Idle	211	Covered	T81,T92,T182
BootLoadGen->RejectCsrngEntropy	188	Covered	T69,T183,T184
BootLoadIns->BootInsAckWait	80	Covered	T2,T3,T23
BootLoadIns->Error	188	Covered	T185,T186,T187
BootLoadIns->Idle	211	Covered	T64,T188,T189
BootLoadIns->RejectCsrngEntropy	188	Covered	T190,T191,T192
BootLoadUni->BootUniAckWait	107	Covered	T3,T23,T56
BootLoadUni->Error	188	Covered	T193,T194,T195
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T196,T197,T198
BootPulse->BootDone	98	Covered	T2,T3,T23
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T86,T199,T200
BootPulse->RejectCsrngEntropy	188	Covered	T201,T202,T203
BootUniAckWait->Error	188	Not Covered
BootUniAckWait->Idle	112	Covered	T23,T56,T59
BootUniAckWait->RejectCsrngEntropy	188	Covered	T3,T122,T204
Idle->AutoLoadIns	69	Covered	T1,T9,T10
Idle->BootLoadIns	65	Covered	T2,T3,T23
Idle->Error	188	Covered	T17,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T1,T84,T39
Idle->SWPortMode	74	Covered	T1,T3,T4
RejectCsrngEntropy->Error	188	Covered	T205,T206,T207
RejectCsrngEntropy->Idle	211	Covered	T1,T3,T23
SWPortMode->Error	188	Covered	T14,T58,T90
SWPortMode->Idle	211	Covered	T1,T3,T4
SWPortMode->RejectCsrngEntropy	188	Covered	T3,T23,T22

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T23
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T23
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T23
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T23
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T23
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T23
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T23
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T23
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T23,T56
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T23,T30
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T56
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T59,T46
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T23,T56
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T9,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T9,T10
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T23
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T30,T31

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T2,T30,T31
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T3,T23
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	211926576	152568	0	0
FpvSecCmErrorStEscalate_A	211926576	153739	0	0
u_state_regs_A	211884524	211692034	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	152568	0	0
T2	625	250	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1072	0	0
T7	0	360	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	602	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	575	0	0
T31	0	341	0	0
T58	0	384	0	0
T80	0	530	0	0
T90	0	348	0	0
T106	0	388	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	153739	0	0
T2	625	251	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1073	0	0
T7	0	361	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	603	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	576	0	0
T31	0	342	0	0
T58	0	385	0	0
T80	0	531	0	0
T90	0	349	0	0
T106	0	389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211884524	211692034	0	0
T1	1765	1680	0	0
T2	504	322	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2098	1941	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0