Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T23
DataWait	75	Covered	T1,T3,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T30,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T86,T199
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T23
DataWait->AckPls	80	Covered	T1,T3,T23
DataWait->Disabled	107	Covered	T81,T129,T155
DataWait->Error	99	Covered	T6,T208,T8
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T5,T96,T209
EndPointClear->Error	99	Covered	T30,T31,T210
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T23
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T14,T58

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T23
Idle	-	1	0	-	Covered	T1,T3,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T23
DataWait	-	-	-	0	Covered	T3,T23,T9
AckPls	-	-	-	-	Covered	T1,T3,T23
Error	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	Covered	T58,T80,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1483486032	1079176	0	0
FpvSecCmErrorStEscalate_A	1483486032	1087373	0	0
u_state_regs_A	1483443980	1482096550	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483486032	1079176	0	0
T2	4375	2100	0	0
T3	18445	0	0	0
T4	12418	0	0	0
T5	242753	0	0	0
T6	0	7504	0	0
T7	0	2470	0	0
T9	45556	0	0	0
T10	32130	0	0	0
T14	0	4214	0	0
T16	15162	0	0	0
T22	12089	0	0	0
T23	14980	0	0	0
T24	11347	0	0	0
T30	0	4375	0	0
T31	0	2737	0	0
T58	0	2638	0	0
T80	0	3660	0	0
T90	0	2386	0	0
T106	0	2666	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483486032	1087373	0	0
T2	4375	2107	0	0
T3	18445	0	0	0
T4	12418	0	0	0
T5	242753	0	0	0
T6	0	7511	0	0
T7	0	2477	0	0
T9	45556	0	0	0
T10	32130	0	0	0
T14	0	4221	0	0
T16	15162	0	0	0
T22	12089	0	0	0
T23	14980	0	0	0
T24	11347	0	0	0
T30	0	4382	0	0
T31	0	2744	0	0
T58	0	2645	0	0
T80	0	3667	0	0
T90	0	2393	0	0
T106	0	2673	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483443980	1482096550	0	0
T1	12355	11760	0	0
T2	4254	2980	0	0
T3	18445	17850	0	0
T4	12418	11627	0	0
T5	242753	237839	0	0
T9	45556	44954	0	0
T10	32130	31668	0	0
T16	15094	13995	0	0
T23	14980	14448	0	0
T24	11347	10969	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T37,T12
DataWait	75	Covered	T23,T37,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T30,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T37,T12
DataWait->AckPls	80	Covered	T23,T37,T12
DataWait->Disabled	107	Covered	T81,T129,T156
DataWait->Error	99	Covered	T8,T181,T51
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T5,T96,T209
EndPointClear->Error	99	Covered	T30,T31,T210
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T37,T12
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T14,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T37,T12
Idle	-	1	0	-	Covered	T23,T37,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T37,T12
DataWait	-	-	-	0	Covered	T23,T37,T12
AckPls	-	-	-	-	Covered	T23,T37,T12
Error	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	211926576	154518	0	0
FpvSecCmErrorStEscalate_A	211926576	155689	0	0
u_state_regs_A	211926576	211734086	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	154518	0	0
T2	625	300	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1072	0	0
T7	0	360	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	602	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	625	0	0
T31	0	391	0	0
T58	0	384	0	0
T80	0	530	0	0
T90	0	348	0	0
T106	0	388	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	155689	0	0
T2	625	301	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1073	0	0
T7	0	361	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	603	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	626	0	0
T31	0	392	0	0
T58	0	385	0	0
T80	0	531	0	0
T90	0	349	0	0
T106	0	389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T37,T12
DataWait	75	Covered	T3,T37,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T30,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T37,T12
DataWait->AckPls	80	Covered	T3,T37,T12
DataWait->Disabled	107	Covered	T155,T182,T211
DataWait->Error	99	Covered	T205,T207,T212
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T5,T96,T209
EndPointClear->Error	99	Covered	T30,T31,T210
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T37,T12
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T14,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T37,T12
Idle	-	1	0	-	Covered	T3,T37,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T37,T12
DataWait	-	-	-	0	Covered	T37,T12,T42
AckPls	-	-	-	-	Covered	T3,T37,T12
Error	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	211926576	154518	0	0
FpvSecCmErrorStEscalate_A	211926576	155689	0	0
u_state_regs_A	211926576	211734086	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	154518	0	0
T2	625	300	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1072	0	0
T7	0	360	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	602	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	625	0	0
T31	0	391	0	0
T58	0	384	0	0
T80	0	530	0	0
T90	0	348	0	0
T106	0	388	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	155689	0	0
T2	625	301	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1073	0	0
T7	0	361	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	603	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	626	0	0
T31	0	392	0	0
T58	0	385	0	0
T80	0	531	0	0
T90	0	349	0	0
T106	0	389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T22,T11
DataWait	75	Covered	T10,T22,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T30,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T22,T11
DataWait->AckPls	80	Covered	T10,T22,T11
DataWait->Disabled	107	Covered	T213,T214,T215
DataWait->Error	99	Covered	T216,T217,T218
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T5,T96,T209
EndPointClear->Error	99	Covered	T30,T31,T210
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T22,T11
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T14,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T22,T11
Idle	-	1	0	-	Covered	T10,T22,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T22,T11
DataWait	-	-	-	0	Covered	T10,T22,T11
AckPls	-	-	-	-	Covered	T10,T22,T11
Error	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	211926576	154518	0	0
FpvSecCmErrorStEscalate_A	211926576	155689	0	0
u_state_regs_A	211926576	211734086	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	154518	0	0
T2	625	300	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1072	0	0
T7	0	360	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	602	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	625	0	0
T31	0	391	0	0
T58	0	384	0	0
T80	0	530	0	0
T90	0	348	0	0
T106	0	388	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	155689	0	0
T2	625	301	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1073	0	0
T7	0	361	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	603	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	626	0	0
T31	0	392	0	0
T58	0	385	0	0
T80	0	531	0	0
T90	0	349	0	0
T106	0	389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T37,T38
DataWait	75	Covered	T10,T37,T38
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T30,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T37,T38
DataWait->AckPls	80	Covered	T10,T37,T38
DataWait->Disabled	107	Covered	T92,T219,T220
DataWait->Error	99	Covered	T15,T140,T221
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T5,T96,T209
EndPointClear->Error	99	Covered	T30,T31,T210
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T37,T38
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T14,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T37,T38
Idle	-	1	0	-	Covered	T10,T37,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T37,T38
DataWait	-	-	-	0	Covered	T10,T37,T38
AckPls	-	-	-	-	Covered	T10,T37,T38
Error	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	211926576	154518	0	0
FpvSecCmErrorStEscalate_A	211926576	155689	0	0
u_state_regs_A	211926576	211734086	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	154518	0	0
T2	625	300	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1072	0	0
T7	0	360	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	602	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	625	0	0
T31	0	391	0	0
T58	0	384	0	0
T80	0	530	0	0
T90	0	348	0	0
T106	0	388	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	155689	0	0
T2	625	301	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1073	0	0
T7	0	361	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	603	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	626	0	0
T31	0	392	0	0
T58	0	385	0	0
T80	0	531	0	0
T90	0	349	0	0
T106	0	389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T9,T10
DataWait	75	Covered	T1,T9,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T30,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T9,T10
DataWait->AckPls	80	Covered	T1,T9,T10
DataWait->Disabled	107	Covered	T98,T222
DataWait->Error	99	Covered	T52,T154,T223
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T5,T96,T209
EndPointClear->Error	99	Covered	T30,T31,T210
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T9,T10
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T14,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T9,T10
Idle	-	1	0	-	Covered	T1,T2,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T9,T10
DataWait	-	-	-	0	Covered	T1,T9,T10
AckPls	-	-	-	-	Covered	T1,T9,T10
Error	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	211926576	154518	0	0
FpvSecCmErrorStEscalate_A	211926576	155689	0	0
u_state_regs_A	211926576	211734086	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	154518	0	0
T2	625	300	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1072	0	0
T7	0	360	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	602	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	625	0	0
T31	0	391	0	0
T58	0	384	0	0
T80	0	530	0	0
T90	0	348	0	0
T106	0	388	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	155689	0	0
T2	625	301	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1073	0	0
T7	0	361	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	603	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	626	0	0
T31	0	392	0	0
T58	0	385	0	0
T80	0	531	0	0
T90	0	349	0	0
T106	0	389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T9,T24
DataWait	75	Covered	T3,T9,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T30,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T199
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T9,T24
DataWait->AckPls	80	Covered	T3,T9,T24
DataWait->Disabled	107	Covered	T224,T225,T226
DataWait->Error	99	Covered	T208,T227,T54
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T5,T96,T209
EndPointClear->Error	99	Covered	T30,T31,T210
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T9,T24
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T14,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T9,T24
Idle	-	1	0	-	Covered	T3,T9,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T9,T24
DataWait	-	-	-	0	Covered	T3,T9,T24
AckPls	-	-	-	-	Covered	T3,T9,T24
Error	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	Covered	T58,T80,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	211926576	152068	0	0
FpvSecCmErrorStEscalate_A	211926576	153239	0	0
u_state_regs_A	211884524	211692034	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	152068	0	0
T2	625	300	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1072	0	0
T7	0	310	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	602	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	625	0	0
T31	0	391	0	0
T58	0	334	0	0
T80	0	480	0	0
T90	0	298	0	0
T106	0	338	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	153239	0	0
T2	625	301	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1073	0	0
T7	0	311	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	603	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	626	0	0
T31	0	392	0	0
T58	0	335	0	0
T80	0	481	0	0
T90	0	299	0	0
T106	0	339	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211884524	211692034	0	0
T1	1765	1680	0	0
T2	504	322	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2098	1941	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T9,T10
DataWait	75	Covered	T1,T9,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T30,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T86
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T9,T10
DataWait->AckPls	80	Covered	T1,T9,T10
DataWait->Disabled	107	Covered	T228,T130,T229
DataWait->Error	99	Covered	T6,T49,T230
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T5,T96,T209
EndPointClear->Error	99	Covered	T30,T31,T210
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T9,T10
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T14,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T9,T10
Idle	-	1	0	-	Covered	T1,T9,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T9,T10
DataWait	-	-	-	0	Covered	T9,T10,T11
AckPls	-	-	-	-	Covered	T1,T9,T10
Error	-	-	-	-	Covered	T2,T30,T31
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	211926576	154518	0	0
FpvSecCmErrorStEscalate_A	211926576	155689	0	0
u_state_regs_A	211926576	211734086	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	154518	0	0
T2	625	300	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1072	0	0
T7	0	360	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	602	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	625	0	0
T31	0	391	0	0
T58	0	384	0	0
T80	0	530	0	0
T90	0	348	0	0
T106	0	388	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	155689	0	0
T2	625	301	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1073	0	0
T7	0	361	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	603	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	626	0	0
T31	0	392	0	0
T58	0	385	0	0
T80	0	531	0	0
T90	0	349	0	0
T106	0	389	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0