Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T16,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T32,T99
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T28,T33
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423088556	1020022	0	0
DepthKnown_A	423853152	423468172	0	0
RvalidKnown_A	423853152	423468172	0	0
WreadyKnown_A	423853152	423468172	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	423457660	1111255	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423088556	1020022	0	0
T1	3530	509	0	0
T2	226	0	0	0
T3	5270	0	0	0
T4	3548	0	0	0
T5	69358	0	0	0
T9	13016	10411	0	0
T10	9180	2989	0	0
T11	0	1032	0	0
T12	0	3077	0	0
T16	1106	0	0	0
T22	0	458	0	0
T23	4280	0	0	0
T24	3242	0	0	0
T43	0	3033	0	0
T56	0	480	0	0
T60	0	853	0	0
T100	0	381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423853152	423468172	0	0
T1	3530	3360	0	0
T2	1250	886	0	0
T3	5270	5100	0	0
T4	3548	3322	0	0
T5	69358	67954	0	0
T9	13016	12844	0	0
T10	9180	9048	0	0
T16	4332	4018	0	0
T23	4280	4128	0	0
T24	3242	3134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423853152	423468172	0	0
T1	3530	3360	0	0
T2	1250	886	0	0
T3	5270	5100	0	0
T4	3548	3322	0	0
T5	69358	67954	0	0
T9	13016	12844	0	0
T10	9180	9048	0	0
T16	4332	4018	0	0
T23	4280	4128	0	0
T24	3242	3134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423853152	423468172	0	0
T1	3530	3360	0	0
T2	1250	886	0	0
T3	5270	5100	0	0
T4	3548	3322	0	0
T5	69358	67954	0	0
T9	13016	12844	0	0
T10	9180	9048	0	0
T16	4332	4018	0	0
T23	4280	4128	0	0
T24	3242	3134	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	423457660	1111255	0	0
T1	3530	509	0	0
T2	1250	222	0	0
T3	5270	0	0	0
T4	3548	0	0	0
T5	69358	0	0	0
T9	13016	10411	0	0
T10	9180	2989	0	0
T11	0	1032	0	0
T12	0	3077	0	0
T16	4332	40	0	0
T22	0	458	0	0
T23	4280	0	0	0
T24	3242	0	0	0
T30	0	268	0	0
T31	0	136	0	0
T43	0	3033	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T10,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T32
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T28,T101
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	211544278	504748	0	0
DepthKnown_A	211926576	211734086	0	0
RvalidKnown_A	211926576	211734086	0	0
WreadyKnown_A	211926576	211734086	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	211728830	550446	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211544278	504748	0	0
T1	1765	256	0	0
T2	113	0	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T9	6508	5197	0	0
T10	4590	1494	0	0
T11	0	478	0	0
T12	0	1470	0	0
T16	553	0	0	0
T22	0	218	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T43	0	1410	0	0
T56	0	245	0	0
T60	0	396	0	0
T100	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	211728830	550446	0	0
T1	1765	256	0	0
T2	625	112	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T9	6508	5197	0	0
T10	4590	1494	0	0
T11	0	478	0	0
T12	0	1470	0	0
T16	2166	40	0	0
T22	0	218	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	135	0	0
T43	0	1410	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T99
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T102,T103
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	211544278	515274	0	0
DepthKnown_A	211926576	211734086	0	0
RvalidKnown_A	211926576	211734086	0	0
WreadyKnown_A	211926576	211734086	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	211728830	560809	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211544278	515274	0	0
T1	1765	253	0	0
T2	113	0	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T9	6508	5214	0	0
T10	4590	1495	0	0
T11	0	554	0	0
T12	0	1607	0	0
T16	553	0	0	0
T22	0	240	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T43	0	1623	0	0
T56	0	235	0	0
T60	0	457	0	0
T100	0	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	211728830	560809	0	0
T1	1765	253	0	0
T2	625	110	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T9	6508	5214	0	0
T10	4590	1495	0	0
T11	0	554	0	0
T12	0	1607	0	0
T16	2166	0	0	0
T22	0	240	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T30	0	133	0	0
T31	0	136	0	0
T43	0	1623	0	0