Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	708033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5782707

1

T1

54244

T2

57

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1708996	1			T1	16015		T2	32		T3	1
values[0x0]	2210975	1			T1	20696		T2	29		T3	1
values[0x1]	2570769	1			T1	23802		T2	26		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	347157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6143583

1

T1

57462

T2

64

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26857	1			T1	197		T22	1		T5	1088
valid_sources[0x01]	26887	1			T1	261		T6	1		T5	1071
valid_sources[0x02]	24257	1			T1	235		T6	2		T9	3
valid_sources[0x03]	24006	1			T1	281		T9	2		T26	1
valid_sources[0x04]	25041	1			T1	193		T26	1		T5	1066
valid_sources[0x05]	23352	1			T1	263		T9	1		T10	2
valid_sources[0x06]	26967	1			T1	268		T5	1036		T38	1
valid_sources[0x07]	23537	1			T1	203		T26	1		T5	954
valid_sources[0x08]	22332	1			T1	253		T22	1		T5	1045
valid_sources[0x09]	25798	1			T1	263		T5	1001		T42	1
valid_sources[0x0a]	27338	1			T1	233		T4	1		T5	955
valid_sources[0x0b]	27491	1			T1	218		T22	1		T5	1060
valid_sources[0x0c]	26894	1			T1	181		T5	964		T36	1
valid_sources[0x0d]	26111	1			T1	289		T5	1014		T75	1
valid_sources[0x0e]	25294	1			T1	251		T9	1		T5	963
valid_sources[0x0f]	24335	1			T1	242		T4	3		T5	1018
valid_sources[0x10]	27566	1			T1	197		T5	975		T36	1
valid_sources[0x11]	24767	1			T1	286		T26	1		T5	1005
valid_sources[0x12]	25435	1			T1	241		T22	2		T10	16
valid_sources[0x13]	25408	1			T1	175		T6	1		T22	2
valid_sources[0x14]	25477	1			T1	264		T6	1		T5	1025
valid_sources[0x15]	25262	1			T1	203		T4	3		T5	1011
valid_sources[0x16]	24911	1			T1	298		T26	1		T5	949
valid_sources[0x17]	23160	1			T1	198		T22	1		T4	1
valid_sources[0x18]	25113	1			T1	264		T22	3		T5	1097
valid_sources[0x19]	24449	1			T1	281		T6	5		T9	1
valid_sources[0x1a]	24491	1			T1	244		T5	998		T49	3
valid_sources[0x1b]	24422	1			T1	250		T6	2		T26	1
valid_sources[0x1c]	26089	1			T1	206		T5	1009		T36	2
valid_sources[0x1d]	24728	1			T1	265		T5	1069		T73	1
valid_sources[0x1e]	25989	1			T1	247		T5	1008		T42	3
valid_sources[0x1f]	23853	1			T1	201		T22	4		T4	1
valid_sources[0x20]	24763	1			T1	210		T6	3		T26	1
valid_sources[0x21]	25582	1			T1	203		T9	1		T5	1017
valid_sources[0x22]	24904	1			T1	232		T6	1		T5	1036
valid_sources[0x23]	24184	1			T1	221		T22	1		T26	1
valid_sources[0x24]	25799	1			T1	234		T22	2		T5	1071
valid_sources[0x25]	24450	1			T1	251		T9	1		T5	1041
valid_sources[0x26]	26355	1			T1	237		T6	1		T5	997
valid_sources[0x27]	26966	1			T1	229		T5	995		T42	1
valid_sources[0x28]	26214	1			T1	261		T6	3		T5	1009
valid_sources[0x29]	26318	1			T1	236		T5	1052		T75	1
valid_sources[0x2a]	25077	1			T1	274		T2	2		T6	1
valid_sources[0x2b]	26481	1			T1	267		T6	1		T22	2
valid_sources[0x2c]	25434	1			T1	239		T2	1		T22	2
valid_sources[0x2d]	25913	1			T1	174		T22	1		T26	1
valid_sources[0x2e]	26714	1			T1	278		T26	1		T5	1029
valid_sources[0x2f]	24745	1			T1	262		T2	2		T9	1
valid_sources[0x30]	26837	1			T1	252		T26	1		T5	1002
valid_sources[0x31]	26678	1			T1	219		T5	1002		T72	4
valid_sources[0x32]	26068	1			T1	277		T22	1		T5	933
valid_sources[0x33]	26438	1			T1	240		T6	2		T26	1
valid_sources[0x34]	26438	1			T1	283		T3	5		T6	1
valid_sources[0x35]	25516	1			T1	251		T4	2		T5	1036
valid_sources[0x36]	25732	1			T1	250		T21	114		T5	1108
valid_sources[0x37]	23602	1			T1	242		T6	1		T9	1
valid_sources[0x38]	26076	1			T1	224		T22	1		T5	1131
valid_sources[0x39]	24064	1			T1	222		T5	1049		T38	1
valid_sources[0x3a]	24362	1			T1	236		T6	1		T5	1071
valid_sources[0x3b]	25512	1			T1	242		T6	2		T9	1
valid_sources[0x3c]	23732	1			T1	196		T22	1		T26	2
valid_sources[0x3d]	25282	1			T1	226		T9	1		T5	1055
valid_sources[0x3e]	28703	1			T1	289		T9	2		T26	1
valid_sources[0x3f]	26606	1			T1	238		T6	3		T10	16
valid_sources[0x40]	25532	1			T1	234		T6	2		T26	1
valid_sources[0x41]	24851	1			T1	169		T6	2		T5	970
valid_sources[0x42]	27060	1			T1	200		T9	1		T22	1
valid_sources[0x43]	26544	1			T1	254		T4	2		T5	1052
valid_sources[0x44]	28205	1			T1	288		T5	1027		T36	3
valid_sources[0x45]	25486	1			T1	198		T5	1096		T38	3
valid_sources[0x46]	25828	1			T1	216		T9	1		T5	962
valid_sources[0x47]	24643	1			T1	229		T22	2		T5	957
valid_sources[0x48]	24777	1			T1	238		T5	985		T36	3
valid_sources[0x49]	24045	1			T1	261		T6	1		T5	984
valid_sources[0x4a]	24601	1			T1	228		T22	1		T5	1045
valid_sources[0x4b]	23817	1			T1	232		T5	983		T36	1
valid_sources[0x4c]	23791	1			T1	283		T2	2		T6	1
valid_sources[0x4d]	25527	1			T1	223		T5	940		T36	7
valid_sources[0x4e]	24887	1			T1	221		T6	3		T22	1
valid_sources[0x4f]	23286	1			T1	200		T9	2		T5	974
valid_sources[0x50]	25594	1			T1	228		T6	1		T9	2
valid_sources[0x51]	25652	1			T1	221		T2	6		T10	12
valid_sources[0x52]	26350	1			T1	220		T9	2		T5	979
valid_sources[0x53]	25579	1			T1	227		T5	967		T36	1
valid_sources[0x54]	23886	1			T1	228		T9	1		T26	1
valid_sources[0x55]	23974	1			T1	237		T9	2		T22	1
valid_sources[0x56]	24712	1			T1	162		T22	1		T4	6
valid_sources[0x57]	25586	1			T1	234		T22	1		T5	1101
valid_sources[0x58]	24587	1			T1	255		T9	1		T5	1063
valid_sources[0x59]	24053	1			T1	215		T6	1		T5	986
valid_sources[0x5a]	24281	1			T1	275		T5	1055		T73	1
valid_sources[0x5b]	24534	1			T1	208		T6	2		T10	4
valid_sources[0x5c]	26884	1			T1	331		T5	1033		T49	1
valid_sources[0x5d]	25967	1			T1	234		T6	1		T9	1
valid_sources[0x5e]	25117	1			T1	293		T47	1		T5	1031
valid_sources[0x5f]	25037	1			T1	240		T6	1		T9	1
valid_sources[0x60]	28316	1			T1	268		T6	2		T22	2
valid_sources[0x61]	28785	1			T1	235		T6	1		T9	2
valid_sources[0x62]	27370	1			T1	213		T9	1		T22	1
valid_sources[0x63]	24267	1			T1	285		T5	1001		T36	1
valid_sources[0x64]	23880	1			T1	307		T4	2		T5	999
valid_sources[0x65]	25297	1			T1	219		T9	1		T26	2
valid_sources[0x66]	27430	1			T1	227		T6	3		T9	1
valid_sources[0x67]	24832	1			T1	291		T5	1039		T42	1
valid_sources[0x68]	25226	1			T1	203		T2	1		T5	962
valid_sources[0x69]	25888	1			T1	223		T9	2		T5	946
valid_sources[0x6a]	25112	1			T1	235		T26	1		T5	1005
valid_sources[0x6b]	26234	1			T1	178		T2	2		T22	3
valid_sources[0x6c]	25068	1			T1	264		T22	1		T5	957
valid_sources[0x6d]	26297	1			T1	187		T2	1		T6	1
valid_sources[0x6e]	26932	1			T1	247		T6	2		T22	1
valid_sources[0x6f]	23802	1			T1	200		T9	1		T22	1
valid_sources[0x70]	25305	1			T1	194		T6	3		T26	2
valid_sources[0x71]	25516	1			T1	213		T6	4		T5	1011
valid_sources[0x72]	23272	1			T1	202		T9	1		T5	1034
valid_sources[0x73]	24191	1			T1	179		T22	2		T47	9
valid_sources[0x74]	27150	1			T1	256		T5	1062		T38	1
valid_sources[0x75]	24605	1			T1	250		T9	1		T47	1
valid_sources[0x76]	24534	1			T1	224		T22	2		T5	1086
valid_sources[0x77]	26615	1			T1	195		T5	1010		T72	1
valid_sources[0x78]	24580	1			T1	266		T2	3		T4	4
valid_sources[0x79]	27069	1			T1	207		T6	1		T9	2
valid_sources[0x7a]	25141	1			T1	250		T6	3		T5	1004
valid_sources[0x7b]	24039	1			T1	262		T6	1		T9	1
valid_sources[0x7c]	25820	1			T1	235		T2	5		T22	3
valid_sources[0x7d]	26530	1			T1	278		T6	1		T22	1
valid_sources[0x7e]	25111	1			T1	211		T22	1		T4	3
valid_sources[0x7f]	27222	1			T1	236		T6	1		T9	3
valid_sources[0x80]	25386	1			T1	230		T26	1		T5	1083

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1456534

1

T1

13728

T2

13

T6

6

values[0x0]

all_enables

biggest_size

2165246

1

T1

20313

T2

25

T3

1

values[0x1]

all_enables

biggest_size

2160927

1

T1

20203

T2

19

T3

1