Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2770	1			T1	18		T6	3		T21	2
non_zero_bins[1]	1915	1			T1	11		T21	1		T9	5
zero	9468	1			T1	64		T2	4		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	525	1			T1	2		T6	1		T5	10
uni	3780	1			T1	29		T6	2		T21	3
gen	4478	1			T1	26		T2	2		T3	1
res	838	1			T1	7		T9	2		T10	1
ins	4532	1			T1	29		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9309

1

T1

67

T2

1

T6

5

mubi_true

4844

1

T1

26

T2

3

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

17

1

T155

1

T90

1

T274

1

pass

14136

1

T1

93

T2

4

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	123	1			T1	1		T6	1		T5	4
upd	non_zero_bins[0]	pass	mubi_true	116	1			T5	2		T87	1		T69	1
upd	non_zero_bins[1]	pass	mubi_false	81	1			T5	2		T71	1		T35	1
upd	non_zero_bins[1]	pass	mubi_true	92	1			T5	1		T38	1		T35	1
upd	zero	pass	mubi_false	59	1			T37	1		T57	1		T226	1
upd	zero	pass	mubi_true	54	1			T1	1		T5	1		T35	2
uni	zero	pass	mubi_false	2777	1			T1	22		T6	2		T21	3
uni	zero	pass	mubi_true	1003	1			T1	7		T5	19		T72	1
gen	non_zero_bins[0]	pass	mubi_false	506	1			T1	1		T6	1		T21	1
gen	non_zero_bins[0]	pass	mubi_true	465	1			T1	2		T22	1		T5	8
gen	non_zero_bins[1]	pass	mubi_false	344	1			T1	3		T5	3		T49	1
gen	non_zero_bins[1]	pass	mubi_true	386	1			T1	3		T9	3		T14	4
gen	zero	fail	mubi_false	13	1			T90	1		T274	1		T275	1
gen	zero	pass	mubi_false	1970	1			T1	16		T10	1		T4	1
gen	zero	pass	mubi_true	794	1			T1	1		T2	2		T3	1
res	non_zero_bins[0]	pass	mubi_false	205	1			T1	2		T5	2		T80	1
res	non_zero_bins[0]	pass	mubi_true	209	1			T1	2		T67	1		T35	3
res	non_zero_bins[1]	pass	mubi_false	142	1			T1	1		T9	2		T14	2
res	non_zero_bins[1]	pass	mubi_true	105	1			T5	2		T76	1		T35	1
res	zero	fail	mubi_false	4	1			T155	1		T276	1		T277	1
res	zero	pass	mubi_false	89	1			T1	1		T10	1		T42	1
res	zero	pass	mubi_true	84	1			T1	1		T5	2		T67	1
ins	non_zero_bins[0]	pass	mubi_false	579	1			T1	4		T6	1		T21	1
ins	non_zero_bins[0]	pass	mubi_true	567	1			T1	6		T5	9		T36	1
ins	non_zero_bins[1]	pass	mubi_false	363	1			T1	2		T21	1		T22	1
ins	non_zero_bins[1]	pass	mubi_true	402	1			T1	2		T22	1		T14	1
ins	zero	pass	mubi_false	2054	1			T1	14		T2	1		T21	1
ins	zero	pass	mubi_true	567	1			T1	1		T2	1		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded