Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T26,T79,T29
1	1	Covered	T3,T6,T21

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T4,T65,T7
1	1	Covered	T2,T9,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T26
1	0	Covered	T4,T29,T7

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T10,T26
1	Covered	T4,T29,T7

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T10,T26
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T10,T4
1	Covered	T4,T29,T7

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T10,T14
AutoCaptGenCnt	143	Covered	T9,T10,T14
AutoCaptReseedCnt	141	Covered	T9,T10,T14
AutoDispatch	125	Covered	T9,T10,T14
AutoFirstAckWait	119	Covered	T9,T10,T14
AutoLoadIns	69	Covered	T2,T9,T10
AutoSendGenCmd	150	Covered	T9,T10,T14
AutoSendReseedCmd	162	Covered	T9,T10,T14
BootDone	98	Covered	T3,T6,T21
BootGenAckWait	90	Covered	T3,T6,T21
BootInsAckWait	80	Covered	T3,T6,T21
BootLoadGen	85	Covered	T3,T6,T21
BootLoadIns	65	Covered	T3,T6,T21
BootLoadUni	102	Covered	T6,T21,T10
BootPulse	94	Covered	T3,T6,T21
BootUniAckWait	107	Covered	T6,T21,T10
Error	188	Covered	T4,T29,T7
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T10,T26
SWPortMode	74	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T10,T14
AutoAckWait->Error	188	Covered	T114,T115,T116
AutoAckWait->Idle	211	Covered	T65,T66,T67
AutoAckWait->RejectCsrngEntropy	188	Covered	T10,T74,T41
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T9,T10,T14
AutoCaptGenCnt->Error	188	Covered	T117
AutoCaptGenCnt->Idle	211	Covered	T118,T119,T120
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T121,T122,T123
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T10,T14
AutoCaptReseedCnt->Error	188	Covered	T8,T124
AutoCaptReseedCnt->Idle	211	Covered	T125,T126,T127
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T128,T129,T130
AutoDispatch->AutoCaptGenCnt	143	Covered	T9,T10,T14
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T10,T14
AutoDispatch->Error	188	Covered	T131,T132,T133
AutoDispatch->Idle	138	Covered	T9,T14,T20
AutoDispatch->RejectCsrngEntropy	188	Covered	T134,T135,T136
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T10,T14
AutoFirstAckWait->Error	188	Covered	T54
AutoFirstAckWait->Idle	211	Covered	T66,T70,T137
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T138,T139,T140
AutoLoadIns->AutoFirstAckWait	119	Covered	T9,T10,T14
AutoLoadIns->Error	188	Covered	T53,T141,T142
AutoLoadIns->Idle	211	Covered	T2,T4,T65
AutoLoadIns->RejectCsrngEntropy	188	Covered	T2,T143,T106
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T10,T14
AutoSendGenCmd->Error	188	Covered	T107,T144,T145
AutoSendGenCmd->Idle	211	Covered	T91,T146,T147
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T86,T148,T108
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T10,T14
AutoSendReseedCmd->Error	188	Covered	T149,T150,T151
AutoSendReseedCmd->Idle	211	Covered	T152,T153,T154
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T60,T155,T156
BootDone->BootLoadUni	102	Covered	T6,T21,T10
BootDone->Error	188	Covered	T157,T158
BootDone->Idle	211	Covered	T159,T160,T161
BootDone->RejectCsrngEntropy	188	Covered	T26,T73,T43
BootGenAckWait->BootPulse	94	Covered	T3,T6,T21
BootGenAckWait->Error	188	Covered	T15,T162,T163
BootGenAckWait->Idle	211	Covered	T29,T164,T165
BootGenAckWait->RejectCsrngEntropy	188	Covered	T111,T109,T166
BootInsAckWait->BootLoadGen	85	Covered	T3,T6,T21
BootInsAckWait->Error	188	Covered	T167,T168,T169
BootInsAckWait->Idle	211	Covered	T15,T61,T55
BootInsAckWait->RejectCsrngEntropy	188	Covered	T170,T171,T172
BootLoadGen->BootGenAckWait	90	Covered	T3,T6,T21
BootLoadGen->Error	188	Covered	T173,T174,T175
BootLoadGen->Idle	211	Covered	T79,T93,T88
BootLoadGen->RejectCsrngEntropy	188	Covered	T176,T177,T178
BootLoadIns->BootInsAckWait	80	Covered	T3,T6,T21
BootLoadIns->Error	188	Covered	T179,T180,T181
BootLoadIns->Idle	211	Covered	T82,T182
BootLoadIns->RejectCsrngEntropy	188	Covered	T47,T183,T184
BootLoadUni->BootUniAckWait	107	Covered	T6,T21,T10
BootLoadUni->Error	188	Covered	T29,T55,T185
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T186,T187
BootPulse->BootDone	98	Covered	T3,T6,T21
BootPulse->Error	188	Covered	T188,T189
BootPulse->Idle	211	Covered	T89,T190,T191
BootPulse->RejectCsrngEntropy	188	Covered	T192,T193,T194
BootUniAckWait->Error	188	Covered	T195,T196
BootUniAckWait->Idle	112	Covered	T6,T21,T10
BootUniAckWait->RejectCsrngEntropy	188	Covered	T46,T197,T105
Idle->AutoLoadIns	69	Covered	T2,T9,T10
Idle->BootLoadIns	65	Covered	T3,T6,T21
Idle->Error	188	Covered	T16,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T43,T103,T60
Idle->SWPortMode	74	Covered	T1,T2,T6
RejectCsrngEntropy->Error	188	Covered	T17,T198,T199
RejectCsrngEntropy->Idle	211	Covered	T2,T10,T26
SWPortMode->Error	188	Covered	T16,T50,T51
SWPortMode->Idle	211	Covered	T1,T26,T47
SWPortMode->RejectCsrngEntropy	188	Covered	T2,T10,T26

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T21,T10
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T3,T10,T26
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T21,T10
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T6,T21,T71
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T21,T10
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T14
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T14
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T14,T20
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T10,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T14
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T26
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T29,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T16

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T29,T7
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T10,T26
0	-	-	1	Covered	T2,T10,T4
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	230618338	155556	0	0
FpvSecCmErrorStEscalate_A	230618338	156848	0	0
u_state_regs_A	230584989	230384951	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	155556	0	0
T4	1140	165	0	0
T5	106977	0	0	0
T7	0	246	0	0
T8	0	635	0	0
T15	0	402	0	0
T16	0	17047	0	0
T17	0	374	0	0
T26	2699	0	0	0
T29	0	644	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	331	0	0
T51	0	238	0	0
T61	0	1073	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	156848	0	0
T4	1140	166	0	0
T5	106977	0	0	0
T7	0	247	0	0
T8	0	636	0	0
T15	0	403	0	0
T16	0	17307	0	0
T17	0	375	0	0
T26	2699	0	0	0
T29	0	645	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	332	0	0
T51	0	239	0	0
T61	0	1074	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230584989	230384951	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	868	755	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0