Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T31,T32
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T33,T34
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460459546	1003237	0	0
DepthKnown_A	461236676	460836600	0	0
RvalidKnown_A	461236676	460836600	0	0
WreadyKnown_A	461236676	460836600	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	460817998	1091699	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460459546	1003237	0	0
T2	4466	331	0	0
T3	1928	0	0	0
T4	604	281	0	0
T6	7108	0	0	0
T7	0	376	0	0
T9	8270	5505	0	0
T10	4118	526	0	0
T14	7216	3763	0	0
T20	0	1751	0	0
T21	5860	0	0	0
T22	3436	0	0	0
T26	5398	0	0	0
T41	0	802	0	0
T65	0	2076	0	0
T74	0	381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461236676	460836600	0	0
T1	329516	329500	0	0
T2	4466	4342	0	0
T3	1928	1764	0	0
T4	2280	2054	0	0
T6	7108	6968	0	0
T9	8270	8118	0	0
T10	4118	4008	0	0
T14	7216	7096	0	0
T21	5860	5722	0	0
T22	3436	3302	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461236676	460836600	0	0
T1	329516	329500	0	0
T2	4466	4342	0	0
T3	1928	1764	0	0
T4	2280	2054	0	0
T6	7108	6968	0	0
T9	8270	8118	0	0
T10	4118	4008	0	0
T14	7216	7096	0	0
T21	5860	5722	0	0
T22	3436	3302	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461236676	460836600	0	0
T1	329516	329500	0	0
T2	4466	4342	0	0
T3	1928	1764	0	0
T4	2280	2054	0	0
T6	7108	6968	0	0
T9	8270	8118	0	0
T10	4118	4008	0	0
T14	7216	7096	0	0
T21	5860	5722	0	0
T22	3436	3302	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	460817998	1091699	0	0
T2	4466	331	0	0
T3	1928	0	0	0
T4	2280	1242	0	0
T6	7108	0	0	0
T9	8270	5505	0	0
T10	4118	526	0	0
T14	7216	3763	0	0
T20	0	1751	0	0
T21	5860	0	0	0
T22	3436	0	0	0
T26	5398	0	0	0
T29	0	453	0	0
T41	0	802	0	0
T65	0	2076	0	0
T74	0	381	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T54,T95
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T31,T96
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T33,T97
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	230229773	495900	0	0
DepthKnown_A	230618338	230418300	0	0
RvalidKnown_A	230618338	230418300	0	0
WreadyKnown_A	230618338	230418300	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	230408999	540022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230229773	495900	0	0
T2	2233	158	0	0
T3	964	0	0	0
T4	302	77	0	0
T6	3554	0	0	0
T7	0	162	0	0
T9	4135	2748	0	0
T10	2059	268	0	0
T14	3608	1878	0	0
T20	0	871	0	0
T21	2930	0	0	0
T22	1718	0	0	0
T26	2699	0	0	0
T41	0	407	0	0
T65	0	981	0	0
T74	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	230408999	540022	0	0
T2	2233	158	0	0
T3	964	0	0	0
T4	1140	568	0	0
T6	3554	0	0	0
T9	4135	2748	0	0
T10	2059	268	0	0
T14	3608	1878	0	0
T20	0	871	0	0
T21	2930	0	0	0
T22	1718	0	0	0
T26	2699	0	0	0
T29	0	232	0	0
T41	0	407	0	0
T65	0	981	0	0
T74	0	192	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T98,T99
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T100,T101
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	230229773	507337	0	0
DepthKnown_A	230618338	230418300	0	0
RvalidKnown_A	230618338	230418300	0	0
WreadyKnown_A	230618338	230418300	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	230408999	551677	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230229773	507337	0	0
T2	2233	173	0	0
T3	964	0	0	0
T4	302	204	0	0
T6	3554	0	0	0
T7	0	214	0	0
T9	4135	2757	0	0
T10	2059	258	0	0
T14	3608	1885	0	0
T20	0	880	0	0
T21	2930	0	0	0
T22	1718	0	0	0
T26	2699	0	0	0
T41	0	395	0	0
T65	0	1095	0	0
T74	0	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	230408999	551677	0	0
T2	2233	173	0	0
T3	964	0	0	0
T4	1140	674	0	0
T6	3554	0	0	0
T9	4135	2757	0	0
T10	2059	258	0	0
T14	3608	1885	0	0
T20	0	880	0	0
T21	2930	0	0	0
T22	1718	0	0	0
T26	2699	0	0	0
T29	0	221	0	0
T41	0	395	0	0
T65	0	1095	0	0
T74	0	189	0	0