Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	140	1			T26	1		T27	1		T39	1
auto_req_mode	147	1			T8	1		T9	1		T15	1
sw_mode	2713	1			T2	76		T21	1		T22	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

279

1

T9

1

T15

1

T27

1

single

121

1

T8

1

T26

1

T40

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1469	1			T2	76		T21	1		T22	1
auto[2]	115	1			T225	50		T300	1		T301	1
auto[3]	31	1			T302	1		T235	17		T303	1
auto[4]	84	1			T4	56		T76	1		T304	12
auto[5]	121	1			T8	1		T95	7		T305	7
auto[6]	35	1			T44	1		T306	24		T307	1
auto[7]	1145	1			T9	1		T40	1		T27	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	83	1			T26	1		T81	1		T97	1
auto[1]	auto_req_mode	81	1			T15	1		T19	1		T69	1
auto[1]	sw_mode	1305	1			T2	76		T21	1		T22	1
auto[2]	boot_req_mode	4	1			T300	1		T308	1		T309	1
auto[2]	auto_req_mode	2	1			T310	1		T311	1		-	-
auto[2]	sw_mode	109	1			T225	50		T301	1		T61	1
auto[3]	boot_req_mode	3	1			T312	1		T313	1		T314	1
auto[3]	auto_req_mode	4	1			T315	1		T316	1		T317	1
auto[3]	sw_mode	24	1			T302	1		T235	17		T303	1
auto[4]	boot_req_mode	3	1			T318	1		T319	1		T320	1
auto[4]	auto_req_mode	5	1			T321	1		T322	1		T323	1
auto[4]	sw_mode	76	1			T4	56		T76	1		T304	12
auto[5]	boot_req_mode	2	1			T324	1		T325	1		-	-
auto[5]	auto_req_mode	3	1			T8	1		T326	1		T327	1
auto[5]	sw_mode	116	1			T95	7		T305	7		T221	44
auto[6]	boot_req_mode	4	1			T44	1		T307	1		T328	1
auto[6]	auto_req_mode	3	1			T329	1		T330	1		T331	1
auto[6]	sw_mode	28	1			T306	24		T332	1		T333	1
auto[7]	boot_req_mode	41	1			T27	1		T39	1		T41	1
auto[7]	auto_req_mode	49	1			T9	1		T10	1		T11	1
auto[7]	sw_mode	1055	1			T40	1		T43	1		T68	22