Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg

Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
66.67	66.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_sw_cmd_sts_cg	66.67	1	100	1	64	64

---

Group Instance : edn_sw_cmd_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance edn_sw_cmd_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	4	8	66.67

Variables for Group Instance edn_sw_cmd_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_cmd_ack_cg	2	0	2	100.00	100	1	1	0
cp_cmd_rdy_cg	2	0	2	100.00	100	1	1	0
cp_cmd_reg_rdy_cg	2	0	2	100.00	100	1	1	0
cp_cmd_sts_cg	6	4	2	33.33	100	1	1	0

Summary for Variable cp_cmd_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_ack_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

no_ack

25524

1

T2

522

T21

1

T22

1

ack

20480

1

T2

549

T21

5

T22

5

---

Summary for Variable cp_cmd_rdy_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_rdy_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_ready

24679

1

T2

519

T4

442

T8

2

ready

21325

1

T2

552

T21

6

T22

6

---

Summary for Variable cp_cmd_reg_rdy_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_reg_rdy_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_ready

464

1

T2

3

T4

9

T8

1

ready

45540

1

T2

1068

T21

6

T22

6

---

Summary for Variable cp_cmd_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	6	4	2	33.33

Automatically Generated Bins for cp_cmd_sts_cg

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[CMD_STS_INVALID_ACMD]	0	1	1
auto[CMD_STS_INVALID_GEN_CMD]	0	1	1
auto[CMD_STS_INVALID_CMD_SEQ]	0	1	1
auto[CMD_STS_UNDRIVEN]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CMD_STS_SUCCESS]	46003	1			T2	1071		T21	6		T22	6
auto[CMD_STS_RESEED_CNT_EXCEEDED]	1	1			T280	1		-	-		-	-