Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	671560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5521614

1

T1

4

T2

57187

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1629939	1			T1	19		T2	20172		T3	44
values[0x0]	2111714	1			T1	9		T2	22011		T3	14
values[0x1]	2451521	1			T1	3		T2	25247		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	329982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5863192

1

T1

7

T2

61684

T3

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25175	1			T2	225		T4	778		T15	3
valid_sources[0x01]	22857	1			T2	190		T20	1		T4	769
valid_sources[0x02]	23553	1			T2	325		T4	798		T9	2
valid_sources[0x03]	25849	1			T2	273		T4	786		T8	1
valid_sources[0x04]	24345	1			T2	220		T22	1		T4	731
valid_sources[0x05]	22602	1			T2	228		T4	732		T8	1
valid_sources[0x06]	25924	1			T2	353		T4	789		T8	1
valid_sources[0x07]	22924	1			T2	180		T22	1		T4	843
valid_sources[0x08]	26357	1			T2	254		T4	829		T24	9
valid_sources[0x09]	24431	1			T2	325		T4	799		T38	362
valid_sources[0x0a]	24556	1			T2	172		T4	759		T9	1
valid_sources[0x0b]	25818	1			T2	261		T4	793		T8	2
valid_sources[0x0c]	24116	1			T2	249		T4	829		T38	128
valid_sources[0x0d]	22725	1			T2	256		T4	773		T9	1
valid_sources[0x0e]	22377	1			T2	260		T4	766		T48	2
valid_sources[0x0f]	24931	1			T2	282		T4	806		T8	1
valid_sources[0x10]	23406	1			T2	235		T4	763		T8	1
valid_sources[0x11]	22797	1			T2	277		T4	800		T40	3
valid_sources[0x12]	22884	1			T2	378		T4	755		T8	2
valid_sources[0x13]	23908	1			T2	201		T4	819		T25	1
valid_sources[0x14]	24701	1			T2	283		T4	783		T40	1
valid_sources[0x15]	25650	1			T2	267		T4	834		T8	1
valid_sources[0x16]	23722	1			T2	268		T4	800		T8	4
valid_sources[0x17]	24821	1			T2	274		T4	773		T8	1
valid_sources[0x18]	24195	1			T2	211		T4	775		T23	1
valid_sources[0x19]	23651	1			T2	300		T4	823		T8	2
valid_sources[0x1a]	24379	1			T2	482		T4	780		T40	1
valid_sources[0x1b]	24209	1			T2	276		T4	804		T8	4
valid_sources[0x1c]	23529	1			T2	307		T4	784		T8	1
valid_sources[0x1d]	24844	1			T2	261		T22	1		T4	803
valid_sources[0x1e]	23055	1			T2	297		T4	824		T47	1
valid_sources[0x1f]	25426	1			T2	197		T4	818		T8	1
valid_sources[0x20]	24195	1			T2	337		T4	792		T40	2
valid_sources[0x21]	27550	1			T2	298		T4	848		T8	1
valid_sources[0x22]	23266	1			T2	246		T22	1		T4	771
valid_sources[0x23]	24370	1			T2	284		T4	778		T9	2
valid_sources[0x24]	22970	1			T2	238		T20	2		T4	845
valid_sources[0x25]	23530	1			T2	240		T4	786		T9	5
valid_sources[0x26]	24637	1			T2	286		T4	824		T8	1
valid_sources[0x27]	25467	1			T2	259		T4	805		T47	2
valid_sources[0x28]	23364	1			T2	225		T4	764		T8	2
valid_sources[0x29]	25826	1			T2	248		T4	765		T8	1
valid_sources[0x2a]	26896	1			T2	294		T4	814		T15	1
valid_sources[0x2b]	22608	1			T2	342		T20	2		T4	804
valid_sources[0x2c]	21877	1			T2	227		T4	838		T9	1
valid_sources[0x2d]	24416	1			T2	374		T22	1		T4	773
valid_sources[0x2e]	24370	1			T2	287		T4	783		T8	2
valid_sources[0x2f]	23688	1			T2	239		T20	2		T22	1
valid_sources[0x30]	25699	1			T2	343		T20	2		T4	818
valid_sources[0x31]	24165	1			T2	224		T4	777		T8	4
valid_sources[0x32]	24961	1			T2	303		T4	747		T15	2
valid_sources[0x33]	23066	1			T2	285		T4	835		T48	7
valid_sources[0x34]	24519	1			T2	285		T4	769		T9	1
valid_sources[0x35]	23296	1			T2	282		T4	798		T9	1
valid_sources[0x36]	22522	1			T2	364		T4	811		T40	2
valid_sources[0x37]	23779	1			T2	186		T4	748		T8	3
valid_sources[0x38]	24387	1			T2	252		T20	2		T4	790
valid_sources[0x39]	24933	1			T2	180		T4	758		T8	5
valid_sources[0x3a]	24284	1			T2	196		T20	1		T4	763
valid_sources[0x3b]	23270	1			T2	261		T4	819		T9	2
valid_sources[0x3c]	24738	1			T2	248		T4	815		T9	1
valid_sources[0x3d]	25356	1			T2	304		T20	1		T4	756
valid_sources[0x3e]	24063	1			T2	305		T4	760		T40	1
valid_sources[0x3f]	23744	1			T2	275		T4	771		T8	3
valid_sources[0x40]	22113	1			T2	346		T4	806		T40	2
valid_sources[0x41]	25850	1			T2	292		T4	789		T9	1
valid_sources[0x42]	24844	1			T2	251		T4	789		T15	2
valid_sources[0x43]	24988	1			T2	242		T4	781		T23	3
valid_sources[0x44]	24077	1			T2	250		T4	804		T25	1
valid_sources[0x45]	24490	1			T2	254		T4	798		T48	3
valid_sources[0x46]	21951	1			T2	267		T4	779		T40	1
valid_sources[0x47]	24724	1			T2	280		T4	828		T8	1
valid_sources[0x48]	24066	1			T2	277		T4	810		T38	214
valid_sources[0x49]	23772	1			T2	285		T4	786		T48	4
valid_sources[0x4a]	26427	1			T2	301		T4	827		T8	2
valid_sources[0x4b]	24561	1			T2	303		T22	1		T4	825
valid_sources[0x4c]	23439	1			T2	299		T4	799		T40	2
valid_sources[0x4d]	25411	1			T2	244		T22	1		T4	759
valid_sources[0x4e]	24158	1			T2	288		T4	801		T40	1
valid_sources[0x4f]	25632	1			T2	245		T4	778		T9	1
valid_sources[0x50]	26294	1			T2	288		T4	782		T48	2
valid_sources[0x51]	24194	1			T2	224		T4	764		T8	3
valid_sources[0x52]	23296	1			T2	227		T20	1		T4	791
valid_sources[0x53]	23271	1			T2	222		T4	765		T40	2
valid_sources[0x54]	24134	1			T2	253		T4	788		T9	1
valid_sources[0x55]	24627	1			T2	267		T3	9		T20	2
valid_sources[0x56]	24526	1			T2	202		T21	30		T4	760
valid_sources[0x57]	26575	1			T2	247		T4	801		T8	2
valid_sources[0x58]	24146	1			T2	247		T3	61		T4	778
valid_sources[0x59]	25529	1			T2	266		T20	2		T4	757
valid_sources[0x5a]	24572	1			T2	279		T4	797		T8	1
valid_sources[0x5b]	24552	1			T2	215		T22	1		T4	740
valid_sources[0x5c]	23095	1			T2	281		T4	813		T8	1
valid_sources[0x5d]	22622	1			T2	292		T4	743		T23	3
valid_sources[0x5e]	22990	1			T2	226		T4	777		T47	2
valid_sources[0x5f]	23600	1			T2	219		T4	794		T15	3
valid_sources[0x60]	24317	1			T2	284		T4	835		T8	1
valid_sources[0x61]	23340	1			T2	232		T4	772		T23	1
valid_sources[0x62]	23707	1			T2	242		T4	778		T8	3
valid_sources[0x63]	23935	1			T2	223		T4	758		T9	2
valid_sources[0x64]	23488	1			T2	266		T4	811		T40	3
valid_sources[0x65]	25015	1			T2	236		T4	798		T48	2
valid_sources[0x66]	23394	1			T2	197		T4	800		T8	1
valid_sources[0x67]	23153	1			T2	278		T4	770		T9	1
valid_sources[0x68]	24369	1			T2	236		T22	1		T4	753
valid_sources[0x69]	24600	1			T2	241		T4	775		T48	12
valid_sources[0x6a]	22584	1			T2	316		T4	786		T8	1
valid_sources[0x6b]	23795	1			T2	273		T4	776		T38	131
valid_sources[0x6c]	24201	1			T2	189		T22	1		T4	753
valid_sources[0x6d]	25508	1			T2	180		T20	1		T4	809
valid_sources[0x6e]	24487	1			T2	217		T4	844		T8	5
valid_sources[0x6f]	24077	1			T2	208		T4	842		T9	4
valid_sources[0x70]	23573	1			T2	220		T4	782		T8	2
valid_sources[0x71]	24324	1			T2	238		T4	856		T38	265
valid_sources[0x72]	23625	1			T2	272		T4	802		T9	1
valid_sources[0x73]	25323	1			T2	243		T4	803		T40	1
valid_sources[0x74]	23305	1			T2	315		T4	819		T38	19
valid_sources[0x75]	24388	1			T2	216		T4	801		T8	3
valid_sources[0x76]	23846	1			T2	243		T4	852		T40	1
valid_sources[0x77]	24105	1			T2	292		T4	802		T8	2
valid_sources[0x78]	23454	1			T2	297		T4	837		T40	4
valid_sources[0x79]	25981	1			T2	372		T4	788		T40	1
valid_sources[0x7a]	23507	1			T2	293		T4	824		T15	2
valid_sources[0x7b]	23917	1			T2	279		T4	776		T9	2
valid_sources[0x7c]	24942	1			T2	251		T20	1		T4	861
valid_sources[0x7d]	22979	1			T2	280		T20	1		T4	801
valid_sources[0x7e]	24968	1			T1	31		T2	303		T4	745
valid_sources[0x7f]	24265	1			T2	209		T4	775		T8	1
valid_sources[0x80]	23152	1			T2	214		T4	786		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1388995

1

T1

2

T2

14521

T3

11

values[0x0]

all_enables

biggest_size

2068442

1

T1

2

T2

21502

T3

8

values[0x1]

all_enables

biggest_size

2064177

1

T2

21164

T3

7

T20

5