Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2547	1			T2	58		T4	26		T8	3
non_zero_bins[1]	1865	1			T2	29		T4	34		T40	1
zero	8939	1			T1	2		T2	189		T3	6

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	454	1			T2	10		T4	5		T48	1
uni	3520	1			T2	89		T21	1		T22	1
gen	4234	1			T1	1		T2	76		T3	3
res	881	1			T2	12		T3	1		T4	12
ins	4262	1			T1	1		T2	89		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8777

1

T1

2

T2

189

T3

3

mubi_true

4574

1

T2

87

T3

3

T20

5

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

18

1

T110

1

T99

1

T102

1

pass

13333

1

T1

2

T2

276

T3

6

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	123	1			T2	3		T4	3		T68	2
upd	non_zero_bins[0]	pass	mubi_true	95	1			T2	3		T4	1		T27	1
upd	non_zero_bins[1]	pass	mubi_false	77	1			T4	1		T38	1		T96	3
upd	non_zero_bins[1]	pass	mubi_true	62	1			T2	2		T97	1		T68	1
upd	zero	pass	mubi_false	50	1			T2	2		T94	3		T96	2
upd	zero	pass	mubi_true	47	1			T48	1		T68	2		T94	3
uni	zero	pass	mubi_false	2632	1			T2	62		T21	1		T22	1
uni	zero	pass	mubi_true	888	1			T2	27		T4	19		T48	4
gen	non_zero_bins[0]	pass	mubi_false	449	1			T2	9		T4	5		T9	1
gen	non_zero_bins[0]	pass	mubi_true	469	1			T2	10		T4	4		T9	3
gen	non_zero_bins[1]	pass	mubi_false	345	1			T2	3		T4	7		T48	1
gen	non_zero_bins[1]	pass	mubi_true	374	1			T2	7		T4	3		T48	1
gen	zero	fail	mubi_false	15	1			T110	1		T99	1		T91	1
gen	zero	pass	mubi_false	1847	1			T1	1		T2	44		T3	1
gen	zero	pass	mubi_true	735	1			T2	3		T3	2		T20	2
res	non_zero_bins[0]	pass	mubi_false	218	1			T2	4		T4	3		T8	2
res	non_zero_bins[0]	pass	mubi_true	197	1			T2	4		T4	1		T48	1
res	non_zero_bins[1]	pass	mubi_false	127	1			T2	2		T4	5		T40	1
res	non_zero_bins[1]	pass	mubi_true	142	1			T4	2		T15	3		T48	2
res	zero	fail	mubi_false	3	1			T102	1		T279	1		T241	1
res	zero	pass	mubi_false	101	1			T3	1		T4	1		T6	1
res	zero	pass	mubi_true	93	1			T2	2		T9	2		T10	2
ins	non_zero_bins[0]	pass	mubi_false	493	1			T2	13		T4	3		T9	1
ins	non_zero_bins[0]	pass	mubi_true	503	1			T2	12		T4	6		T8	1
ins	non_zero_bins[1]	pass	mubi_false	357	1			T2	4		T4	8		T48	1
ins	non_zero_bins[1]	pass	mubi_true	381	1			T2	11		T4	8		T27	1
ins	zero	pass	mubi_false	1940	1			T1	1		T2	43		T3	1
ins	zero	pass	mubi_true	588	1			T2	6		T3	1		T20	3

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded