Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T81,T101
1	1	Covered	T20,T26,T27

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T5,T6
1	1	Covered	T3,T8,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T20,T29
1	0	Covered	T1,T29,T34

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T3,T20,T29
1	Covered	T1,T29,T34

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T3,T20,T29
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T20
1	Covered	T1,T29,T34

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T20,T26

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T3,T8,T9
AutoCaptGenCnt	143	Covered	T3,T8,T9
AutoCaptReseedCnt	141	Covered	T3,T8,T9
AutoDispatch	125	Covered	T3,T8,T9
AutoFirstAckWait	119	Covered	T3,T8,T9
AutoLoadIns	69	Covered	T3,T8,T9
AutoSendGenCmd	150	Covered	T3,T8,T9
AutoSendReseedCmd	162	Covered	T3,T8,T9
BootDone	98	Covered	T20,T26,T27
BootGenAckWait	90	Covered	T20,T26,T27
BootInsAckWait	80	Covered	T20,T26,T27
BootLoadGen	85	Covered	T20,T26,T27
BootLoadIns	65	Covered	T20,T26,T27
BootLoadUni	102	Covered	T20,T27,T28
BootPulse	94	Covered	T20,T26,T27
BootUniAckWait	107	Covered	T20,T27,T28
Error	188	Covered	T1,T29,T34
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T3,T20,T29
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T3,T8,T9
AutoAckWait->Error	188	Not Covered
AutoAckWait->Idle	211	Covered	T15,T69,T111
AutoAckWait->RejectCsrngEntropy	188	Covered	T3,T110,T99
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T3,T8,T9
AutoCaptGenCnt->Error	188	Covered	T112,T113,T114
AutoCaptGenCnt->Idle	211	Covered	T115,T116,T117
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T82,T103,T118
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T3,T8,T9
AutoCaptReseedCnt->Error	188	Covered	T119,T120
AutoCaptReseedCnt->Idle	211	Covered	T121,T122,T123
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T124,T125,T126
AutoDispatch->AutoCaptGenCnt	143	Covered	T3,T8,T9
AutoDispatch->AutoCaptReseedCnt	141	Covered	T3,T8,T9
AutoDispatch->Error	188	Covered	T127,T128,T129
AutoDispatch->Idle	138	Covered	T8,T9,T15
AutoDispatch->RejectCsrngEntropy	188	Covered	T104,T130,T131
AutoFirstAckWait->AutoDispatch	125	Covered	T3,T8,T9
AutoFirstAckWait->Error	188	Covered	T72,T132,T133
AutoFirstAckWait->Idle	211	Covered	T69,T134,T135
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T78,T136,T137
AutoLoadIns->AutoFirstAckWait	119	Covered	T3,T8,T9
AutoLoadIns->Error	188	Covered	T7,T51,T52
AutoLoadIns->Idle	211	Covered	T45,T5,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T138,T139,T140
AutoSendGenCmd->AutoAckWait	156	Covered	T3,T8,T9
AutoSendGenCmd->Error	188	Covered	T141,T142,T143
AutoSendGenCmd->Idle	211	Covered	T144,T145,T146
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T147,T148,T149
AutoSendReseedCmd->AutoAckWait	168	Covered	T3,T8,T9
AutoSendReseedCmd->Error	188	Covered	T13,T49,T150
AutoSendReseedCmd->Idle	211	Covered	T151,T152,T153
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T102,T107,T154
BootDone->BootLoadUni	102	Covered	T20,T27,T28
BootDone->Error	188	Covered	T155,T156
BootDone->Idle	211	Covered	T26,T157,T158
BootDone->RejectCsrngEntropy	188	Covered	T159,T160,T161
BootGenAckWait->BootPulse	94	Covered	T20,T26,T27
BootGenAckWait->Error	188	Covered	T162,T163,T164
BootGenAckWait->Idle	211	Covered	T86,T87,T155
BootGenAckWait->RejectCsrngEntropy	188	Covered	T20,T101,T105
BootInsAckWait->BootLoadGen	85	Covered	T20,T26,T27
BootInsAckWait->Error	188	Covered	T165,T58,T166
BootInsAckWait->Idle	211	Covered	T167,T165,T168
BootInsAckWait->RejectCsrngEntropy	188	Covered	T75,T169,T100
BootLoadGen->BootGenAckWait	90	Covered	T20,T26,T27
BootLoadGen->Error	188	Not Covered
BootLoadGen->Idle	211	Covered	T81,T88,T170
BootLoadGen->RejectCsrngEntropy	188	Covered	T45,T77,T171
BootLoadIns->BootInsAckWait	80	Covered	T20,T26,T27
BootLoadIns->Error	188	Covered	T172,T173,T54
BootLoadIns->Idle	211	Covered	T174,T175,T176
BootLoadIns->RejectCsrngEntropy	188	Covered	T177,T178,T179
BootLoadUni->BootUniAckWait	107	Covered	T20,T27,T28
BootLoadUni->Error	188	Covered	T180
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T79,T181,T182
BootPulse->BootDone	98	Covered	T20,T26,T27
BootPulse->Error	188	Covered	T183
BootPulse->Idle	211	Covered	T184,T185,T186
BootPulse->RejectCsrngEntropy	188	Covered	T187,T188,T189
BootUniAckWait->Error	188	Covered	T190
BootUniAckWait->Idle	112	Covered	T20,T27,T39
BootUniAckWait->RejectCsrngEntropy	188	Covered	T28,T191,T192
Idle->AutoLoadIns	69	Covered	T3,T8,T9
Idle->BootLoadIns	65	Covered	T20,T26,T27
Idle->Error	188	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T20,T45,T82
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T29,T193,T194
RejectCsrngEntropy->Idle	211	Covered	T3,T20,T28
SWPortMode->Error	188	Covered	T1,T34,T14
SWPortMode->Idle	211	Covered	T2,T3,T4
SWPortMode->RejectCsrngEntropy	188	Covered	T3,T29,T28

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T26,T27
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T26,T27
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T26,T27
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T20,T26,T27
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T26,T27
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T20,T26,T27
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T20,T26,T27
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T26,T27
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T27,T28
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T20,T26,T81
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T27,T28
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T27,T28,T39
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T20,T27,T28
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T8,T9
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T8,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T8,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T8,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T8,T9,T19
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T8,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T8,T9
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T8,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T9,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T8,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T9,T15
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T29
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T34
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T46,T5,T6

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T29,T34
1	0	1	-	Not Covered
1	0	0	-	Covered	T3,T20,T29
0	-	-	1	Covered	T3,T20,T26
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	208936469	123315	0	0
FpvSecCmErrorStEscalate_A	208936469	124097	0	0
u_state_regs_A	208901410	208742004	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936469	123315	0	0
T1	1033	417	0	0
T2	188174	0	0	0
T3	3050	0	0	0
T4	945335	0	0	0
T5	0	349	0	0
T6	0	560	0	0
T7	0	270	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T20	2209	0	0	0
T21	1655	0	0	0
T22	1332	0	0	0
T23	1915	0	0	0
T29	0	415	0	0
T34	0	1110	0	0
T46	0	960	0	0
T71	0	325	0	0
T72	0	915	0	0
T73	0	300	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936469	124097	0	0
T1	1033	418	0	0
T2	188174	0	0	0
T3	3050	0	0	0
T4	945335	0	0	0
T5	0	350	0	0
T6	0	561	0	0
T7	0	271	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T20	2209	0	0	0
T21	1655	0	0	0
T22	1332	0	0	0
T23	1915	0	0	0
T29	0	416	0	0
T34	0	1111	0	0
T46	0	961	0	0
T71	0	326	0	0
T72	0	916	0	0
T73	0	301	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208901410	208742004	0	0
T1	852	710	0	0
T2	188174	188162	0	0
T3	3050	2997	0	0
T4	945335	945325	0	0
T8	5418	5339	0	0
T9	3130	3046	0	0
T20	2209	2154	0	0
T21	1655	1571	0	0
T22	1332	1245	0	0
T23	1915	1832	0	0