Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T36,T90
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T31,T37
1	0	1	Covered	T3,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417261092	1097217	0	0
DepthKnown_A	417872938	417554126	0	0
RvalidKnown_A	417872938	417554126	0	0
WreadyKnown_A	417872938	417554126	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	417627754	1186560	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417261092	1097217	0	0
T3	6100	736	0	0
T4	1890670	0	0	0
T5	0	278	0	0
T6	0	65	0	0
T8	10836	5723	0	0
T9	6260	3506	0	0
T15	0	2150	0	0
T19	0	1026	0	0
T20	4418	0	0	0
T21	3310	0	0	0
T22	2664	0	0	0
T23	3830	0	0	0
T26	1880	0	0	0
T40	3998	0	0	0
T45	0	260	0	0
T78	0	975	0	0
T82	0	432	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417872938	417554126	0	0
T1	2066	1782	0	0
T2	376348	376324	0	0
T3	6100	5994	0	0
T4	1890670	1890650	0	0
T8	10836	10678	0	0
T9	6260	6092	0	0
T20	4418	4308	0	0
T21	3310	3142	0	0
T22	2664	2490	0	0
T23	3830	3664	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417872938	417554126	0	0
T1	2066	1782	0	0
T2	376348	376324	0	0
T3	6100	5994	0	0
T4	1890670	1890650	0	0
T8	10836	10678	0	0
T9	6260	6092	0	0
T20	4418	4308	0	0
T21	3310	3142	0	0
T22	2664	2490	0	0
T23	3830	3664	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417872938	417554126	0	0
T1	2066	1782	0	0
T2	376348	376324	0	0
T3	6100	5994	0	0
T4	1890670	1890650	0	0
T8	10836	10678	0	0
T9	6260	6092	0	0
T20	4418	4308	0	0
T21	3310	3142	0	0
T22	2664	2490	0	0
T23	3830	3664	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	417627754	1186560	0	0
T3	6100	736	0	0
T4	1890670	0	0	0
T5	0	1239	0	0
T8	10836	5723	0	0
T9	6260	3506	0	0
T15	0	2150	0	0
T20	4418	0	0	0
T21	3310	0	0	0
T22	2664	0	0	0
T23	3830	0	0	0
T26	1880	0	0	0
T29	0	372	0	0
T34	0	220	0	0
T40	3998	0	0	0
T45	0	260	0	0
T46	0	422	0	0
T82	0	432	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T73,T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T90,T92
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T37,T93
1	0	1	Covered	T3,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	208630546	541878	0	0
DepthKnown_A	208936469	208777063	0	0
RvalidKnown_A	208936469	208777063	0	0
WreadyKnown_A	208936469	208777063	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	208813877	586193	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208630546	541878	0	0
T3	3050	372	0	0
T4	945335	0	0	0
T5	0	106	0	0
T6	0	27	0	0
T8	5418	2833	0	0
T9	3130	1712	0	0
T15	0	1058	0	0
T19	0	498	0	0
T20	2209	0	0	0
T21	1655	0	0	0
T22	1332	0	0	0
T23	1915	0	0	0
T26	940	0	0	0
T40	1999	0	0	0
T45	0	80	0	0
T78	0	477	0	0
T82	0	217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936469	208777063	0	0
T1	1033	891	0	0
T2	188174	188162	0	0
T3	3050	2997	0	0
T4	945335	945325	0	0
T8	5418	5339	0	0
T9	3130	3046	0	0
T20	2209	2154	0	0
T21	1655	1571	0	0
T22	1332	1245	0	0
T23	1915	1832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936469	208777063	0	0
T1	1033	891	0	0
T2	188174	188162	0	0
T3	3050	2997	0	0
T4	945335	945325	0	0
T8	5418	5339	0	0
T9	3130	3046	0	0
T20	2209	2154	0	0
T21	1655	1571	0	0
T22	1332	1245	0	0
T23	1915	1832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936469	208777063	0	0
T1	1033	891	0	0
T2	188174	188162	0	0
T3	3050	2997	0	0
T4	945335	945325	0	0
T8	5418	5339	0	0
T9	3130	3046	0	0
T20	2209	2154	0	0
T21	1655	1571	0	0
T22	1332	1245	0	0
T23	1915	1832	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	208813877	586193	0	0
T3	3050	372	0	0
T4	945335	0	0	0
T5	0	554	0	0
T8	5418	2833	0	0
T9	3130	1712	0	0
T15	0	1058	0	0
T20	2209	0	0	0
T21	1655	0	0	0
T22	1332	0	0	0
T23	1915	0	0	0
T26	940	0	0	0
T29	0	189	0	0
T34	0	111	0	0
T40	1999	0	0	0
T45	0	80	0	0
T46	0	212	0	0
T82	0	217	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T36
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33
1	0	1	Covered	T3,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	208630546	555339	0	0
DepthKnown_A	208936469	208777063	0	0
RvalidKnown_A	208936469	208777063	0	0
WreadyKnown_A	208936469	208777063	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	208813877	600367	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208630546	555339	0	0
T3	3050	364	0	0
T4	945335	0	0	0
T5	0	172	0	0
T6	0	38	0	0
T8	5418	2890	0	0
T9	3130	1794	0	0
T15	0	1092	0	0
T19	0	528	0	0
T20	2209	0	0	0
T21	1655	0	0	0
T22	1332	0	0	0
T23	1915	0	0	0
T26	940	0	0	0
T40	1999	0	0	0
T45	0	180	0	0
T78	0	498	0	0
T82	0	215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936469	208777063	0	0
T1	1033	891	0	0
T2	188174	188162	0	0
T3	3050	2997	0	0
T4	945335	945325	0	0
T8	5418	5339	0	0
T9	3130	3046	0	0
T20	2209	2154	0	0
T21	1655	1571	0	0
T22	1332	1245	0	0
T23	1915	1832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936469	208777063	0	0
T1	1033	891	0	0
T2	188174	188162	0	0
T3	3050	2997	0	0
T4	945335	945325	0	0
T8	5418	5339	0	0
T9	3130	3046	0	0
T20	2209	2154	0	0
T21	1655	1571	0	0
T22	1332	1245	0	0
T23	1915	1832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936469	208777063	0	0
T1	1033	891	0	0
T2	188174	188162	0	0
T3	3050	2997	0	0
T4	945335	945325	0	0
T8	5418	5339	0	0
T9	3130	3046	0	0
T20	2209	2154	0	0
T21	1655	1571	0	0
T22	1332	1245	0	0
T23	1915	1832	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	208813877	600367	0	0
T3	3050	364	0	0
T4	945335	0	0	0
T5	0	685	0	0
T8	5418	2890	0	0
T9	3130	1794	0	0
T15	0	1092	0	0
T20	2209	0	0	0
T21	1655	0	0	0
T22	1332	0	0	0
T23	1915	0	0	0
T26	940	0	0	0
T29	0	183	0	0
T34	0	109	0	0
T40	1999	0	0	0
T45	0	180	0	0
T46	0	210	0	0
T82	0	215	0	0