Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	124	1			T62	1		T37	1		T199	1
auto_req_mode	144	1			T9	1		T10	1		T12	1
sw_mode	2996	1			T3	1		T5	60		T23	13

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

302

1

T3

1

T10

1

T12

1

single

98

1

T9

1

T199

1

T45

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1501	1			T9	1		T10	1		T36	1
auto[2]	119	1			T12	1		T37	1		T69	1
auto[3]	142	1			T308	1		T309	1		T310	1
auto[4]	192	1			T311	1		T312	1		T313	56
auto[5]	133	1			T61	7		T74	1		T314	1
auto[6]	33	1			T42	1		T315	1		T316	1
auto[7]	1144	1			T3	1		T5	60		T23	13

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	77	1			T62	1		T199	1		T186	1
auto[1]	auto_req_mode	90	1			T9	1		T10	1		T36	1
auto[1]	sw_mode	1334	1			T59	1		T60	1		T76	1
auto[2]	boot_req_mode	4	1			T37	1		T317	1		T318	1
auto[2]	auto_req_mode	4	1			T12	1		T292	1		T14	1
auto[2]	sw_mode	111	1			T69	1		T70	1		T226	76
auto[3]	boot_req_mode	4	1			T319	1		T320	1		T321	1
auto[3]	auto_req_mode	6	1			T308	1		T310	1		T322	1
auto[3]	sw_mode	132	1			T309	1		T323	1		T324	1
auto[4]	boot_req_mode	5	1			T325	1		T326	1		T327	1
auto[4]	auto_req_mode	1	1			T328	1		-	-		-	-
auto[4]	sw_mode	186	1			T311	1		T312	1		T313	56
auto[5]	boot_req_mode	1	1			T329	1		-	-		-	-
auto[5]	auto_req_mode	3	1			T74	1		T314	1		T330	1
auto[5]	sw_mode	129	1			T61	7		T331	1		T332	1
auto[6]	boot_req_mode	3	1			T316	1		T333	1		T334	1
auto[6]	auto_req_mode	3	1			T315	1		T335	1		T336	1
auto[6]	sw_mode	27	1			T42	1		T337	1		T338	1
auto[7]	boot_req_mode	30	1			T40	1		T41	1		T71	1
auto[7]	auto_req_mode	37	1			T19	1		T21	1		T48	1
auto[7]	sw_mode	1077	1			T3	1		T5	60		T23	13